/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * x1000 version: 1.0
 * x1000 authors: Aidan MacDonald
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_DDRPHY_H__
#define __HEADERGEN_DDRPHY_H__

#include "macro.h"

#define REG_DDRPHY_PIR  jz_reg(DDRPHY_PIR)
#define JA_DDRPHY_PIR   (0xb3011000 + 0x4)
#define JT_DDRPHY_PIR   JIO_32_RW
#define JN_DDRPHY_PIR   DDRPHY_PIR
#define JI_DDRPHY_PIR   

#define REG_DDRPHY_PGCR jz_reg(DDRPHY_PGCR)
#define JA_DDRPHY_PGCR  (0xb3011000 + 0x8)
#define JT_DDRPHY_PGCR  JIO_32_RW
#define JN_DDRPHY_PGCR  DDRPHY_PGCR
#define JI_DDRPHY_PGCR  

#define REG_DDRPHY_PGSR jz_reg(DDRPHY_PGSR)
#define JA_DDRPHY_PGSR  (0xb3011000 + 0xc)
#define JT_DDRPHY_PGSR  JIO_32_RW
#define JN_DDRPHY_PGSR  DDRPHY_PGSR
#define JI_DDRPHY_PGSR  

#define REG_DDRPHY_DLLGCR   jz_reg(DDRPHY_DLLGCR)
#define JA_DDRPHY_DLLGCR    (0xb3011000 + 0x10)
#define JT_DDRPHY_DLLGCR    JIO_32_RW
#define JN_DDRPHY_DLLGCR    DDRPHY_DLLGCR
#define JI_DDRPHY_DLLGCR    

#define REG_DDRPHY_ACDLLCR  jz_reg(DDRPHY_ACDLLCR)
#define JA_DDRPHY_ACDLLCR   (0xb3011000 + 0x14)
#define JT_DDRPHY_ACDLLCR   JIO_32_RW
#define JN_DDRPHY_ACDLLCR   DDRPHY_ACDLLCR
#define JI_DDRPHY_ACDLLCR   

#define REG_DDRPHY_PTR0 jz_reg(DDRPHY_PTR0)
#define JA_DDRPHY_PTR0  (0xb3011000 + 0x18)
#define JT_DDRPHY_PTR0  JIO_32_RW
#define JN_DDRPHY_PTR0  DDRPHY_PTR0
#define JI_DDRPHY_PTR0  

#define REG_DDRPHY_PTR1 jz_reg(DDRPHY_PTR1)
#define JA_DDRPHY_PTR1  (0xb3011000 + 0x1c)
#define JT_DDRPHY_PTR1  JIO_32_RW
#define JN_DDRPHY_PTR1  DDRPHY_PTR1
#define JI_DDRPHY_PTR1  

#define REG_DDRPHY_PTR2 jz_reg(DDRPHY_PTR2)
#define JA_DDRPHY_PTR2  (0xb3011000 + 0x20)
#define JT_DDRPHY_PTR2  JIO_32_RW
#define JN_DDRPHY_PTR2  DDRPHY_PTR2
#define JI_DDRPHY_PTR2  

#define REG_DDRPHY_ACIOCR   jz_reg(DDRPHY_ACIOCR)
#define JA_DDRPHY_ACIOCR    (0xb3011000 + 0x24)
#define JT_DDRPHY_ACIOCR    JIO_32_RW
#define JN_DDRPHY_ACIOCR    DDRPHY_ACIOCR
#define JI_DDRPHY_ACIOCR    

#define REG_DDRPHY_DXCCR    jz_reg(DDRPHY_DXCCR)
#define JA_DDRPHY_DXCCR     (0xb3011000 + 0x28)
#define JT_DDRPHY_DXCCR     JIO_32_RW
#define JN_DDRPHY_DXCCR     DDRPHY_DXCCR
#define JI_DDRPHY_DXCCR     

#define REG_DDRPHY_DSGCR    jz_reg(DDRPHY_DSGCR)
#define JA_DDRPHY_DSGCR     (0xb3011000 + 0x2c)
#define JT_DDRPHY_DSGCR     JIO_32_RW
#define JN_DDRPHY_DSGCR     DDRPHY_DSGCR
#define JI_DDRPHY_DSGCR     

#define REG_DDRPHY_DCR  jz_reg(DDRPHY_DCR)
#define JA_DDRPHY_DCR   (0xb3011000 + 0x30)
#define JT_DDRPHY_DCR   JIO_32_RW
#define JN_DDRPHY_DCR   DDRPHY_DCR
#define JI_DDRPHY_DCR   

#define REG_DDRPHY_DTPR0    jz_reg(DDRPHY_DTPR0)
#define JA_DDRPHY_DTPR0     (0xb3011000 + 0x34)
#define JT_DDRPHY_DTPR0     JIO_32_RW
#define JN_DDRPHY_DTPR0     DDRPHY_DTPR0
#define JI_DDRPHY_DTPR0     

#define REG_DDRPHY_DTPR1    jz_reg(DDRPHY_DTPR1)
#define JA_DDRPHY_DTPR1     (0xb3011000 + 0x38)
#define JT_DDRPHY_DTPR1     JIO_32_RW
#define JN_DDRPHY_DTPR1     DDRPHY_DTPR1
#define JI_DDRPHY_DTPR1     

#define REG_DDRPHY_DTPR2    jz_reg(DDRPHY_DTPR2)
#define JA_DDRPHY_DTPR2     (0xb3011000 + 0x3c)
#define JT_DDRPHY_DTPR2     JIO_32_RW
#define JN_DDRPHY_DTPR2     DDRPHY_DTPR2
#define JI_DDRPHY_DTPR2     

#define REG_DDRPHY_MR0  jz_reg(DDRPHY_MR0)
#define JA_DDRPHY_MR0   (0xb3011000 + 0x40)
#define JT_DDRPHY_MR0   JIO_32_RW
#define JN_DDRPHY_MR0   DDRPHY_MR0
#define JI_DDRPHY_MR0   

#define REG_DDRPHY_MR1  jz_reg(DDRPHY_MR1)
#define JA_DDRPHY_MR1   (0xb3011000 + 0x44)
#define JT_DDRPHY_MR1   JIO_32_RW
#define JN_DDRPHY_MR1   DDRPHY_MR1
#define JI_DDRPHY_MR1   

#define REG_DDRPHY_MR2  jz_reg(DDRPHY_MR2)
#define JA_DDRPHY_MR2   (0xb3011000 + 0x48)
#define JT_DDRPHY_MR2   JIO_32_RW
#define JN_DDRPHY_MR2   DDRPHY_MR2
#define JI_DDRPHY_MR2   

#define REG_DDRPHY_MR3  jz_reg(DDRPHY_MR3)
#define JA_DDRPHY_MR3   (0xb3011000 + 0x4c)
#define JT_DDRPHY_MR3   JIO_32_RW
#define JN_DDRPHY_MR3   DDRPHY_MR3
#define JI_DDRPHY_MR3   

#define REG_DDRPHY_DTAR jz_reg(DDRPHY_DTAR)
#define JA_DDRPHY_DTAR  (0xb3011000 + 0x54)
#define JT_DDRPHY_DTAR  JIO_32_RW
#define JN_DDRPHY_DTAR  DDRPHY_DTAR
#define JI_DDRPHY_DTAR  

#define REG_DDRPHY_DXGCR(_n1)   jz_reg(DDRPHY_DXGCR(_n1))
#define JA_DDRPHY_DXGCR(_n1)    (0xb3011000 + 0x1c0 + (_n1) * 0x40)
#define JT_DDRPHY_DXGCR(_n1)    JIO_32_RW
#define JN_DDRPHY_DXGCR(_n1)    DDRPHY_DXGCR
#define JI_DDRPHY_DXGCR(_n1)    (_n1)

#endif /* __HEADERGEN_DDRPHY_H__*/
