/***************************************************************************
 *             __________               __   ___.
 *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
 *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
 *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
 *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
 *                     \/            \/     \/    \/            \/
 * This file was automatically generated by headergen, DO NOT EDIT it.
 * headergen version: 3.0.0
 * imx233 version: 2.4.0
 * imx233 authors: Amaury Pouly
 *
 * Copyright (C) 2015 by the authors
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
 * KIND, either express or implied.
 *
 ****************************************************************************/
#ifndef __HEADERGEN_IMX233_EMI_H__
#define __HEADERGEN_IMX233_EMI_H__

#define HW_EMI_CTRL                                 HW(EMI_CTRL)
#define HWA_EMI_CTRL                                (0x80020000 + 0x0)
#define HWT_EMI_CTRL                                HWIO_32_RW
#define HWN_EMI_CTRL                                EMI_CTRL
#define HWI_EMI_CTRL                                
#define HW_EMI_CTRL_SET                             HW(EMI_CTRL_SET)
#define HWA_EMI_CTRL_SET                            (HWA_EMI_CTRL + 0x4)
#define HWT_EMI_CTRL_SET                            HWIO_32_WO
#define HWN_EMI_CTRL_SET                            EMI_CTRL
#define HWI_EMI_CTRL_SET                            
#define HW_EMI_CTRL_CLR                             HW(EMI_CTRL_CLR)
#define HWA_EMI_CTRL_CLR                            (HWA_EMI_CTRL + 0x8)
#define HWT_EMI_CTRL_CLR                            HWIO_32_WO
#define HWN_EMI_CTRL_CLR                            EMI_CTRL
#define HWI_EMI_CTRL_CLR                            
#define HW_EMI_CTRL_TOG                             HW(EMI_CTRL_TOG)
#define HWA_EMI_CTRL_TOG                            (HWA_EMI_CTRL + 0xc)
#define HWT_EMI_CTRL_TOG                            HWIO_32_WO
#define HWN_EMI_CTRL_TOG                            EMI_CTRL
#define HWI_EMI_CTRL_TOG                            
#define BP_EMI_CTRL_SFTRST                          31
#define BM_EMI_CTRL_SFTRST                          0x80000000
#define BF_EMI_CTRL_SFTRST(v)                       (((v) & 0x1) << 31)
#define BFM_EMI_CTRL_SFTRST(v)                      BM_EMI_CTRL_SFTRST
#define BF_EMI_CTRL_SFTRST_V(e)                     BF_EMI_CTRL_SFTRST(BV_EMI_CTRL_SFTRST__##e)
#define BFM_EMI_CTRL_SFTRST_V(v)                    BM_EMI_CTRL_SFTRST
#define BP_EMI_CTRL_CLKGATE                         30
#define BM_EMI_CTRL_CLKGATE                         0x40000000
#define BF_EMI_CTRL_CLKGATE(v)                      (((v) & 0x1) << 30)
#define BFM_EMI_CTRL_CLKGATE(v)                     BM_EMI_CTRL_CLKGATE
#define BF_EMI_CTRL_CLKGATE_V(e)                    BF_EMI_CTRL_CLKGATE(BV_EMI_CTRL_CLKGATE__##e)
#define BFM_EMI_CTRL_CLKGATE_V(v)                   BM_EMI_CTRL_CLKGATE
#define BP_EMI_CTRL_TRAP_SR                         29
#define BM_EMI_CTRL_TRAP_SR                         0x20000000
#define BF_EMI_CTRL_TRAP_SR(v)                      (((v) & 0x1) << 29)
#define BFM_EMI_CTRL_TRAP_SR(v)                     BM_EMI_CTRL_TRAP_SR
#define BF_EMI_CTRL_TRAP_SR_V(e)                    BF_EMI_CTRL_TRAP_SR(BV_EMI_CTRL_TRAP_SR__##e)
#define BFM_EMI_CTRL_TRAP_SR_V(v)                   BM_EMI_CTRL_TRAP_SR
#define BP_EMI_CTRL_TRAP_INIT                       28
#define BM_EMI_CTRL_TRAP_INIT                       0x10000000
#define BF_EMI_CTRL_TRAP_INIT(v)                    (((v) & 0x1) << 28)
#define BFM_EMI_CTRL_TRAP_INIT(v)                   BM_EMI_CTRL_TRAP_INIT
#define BF_EMI_CTRL_TRAP_INIT_V(e)                  BF_EMI_CTRL_TRAP_INIT(BV_EMI_CTRL_TRAP_INIT__##e)
#define BFM_EMI_CTRL_TRAP_INIT_V(v)                 BM_EMI_CTRL_TRAP_INIT
#define BP_EMI_CTRL_AXI_DEPTH                       26
#define BM_EMI_CTRL_AXI_DEPTH                       0xc000000
#define BV_EMI_CTRL_AXI_DEPTH__ONE                  0x0
#define BV_EMI_CTRL_AXI_DEPTH__TWO                  0x1
#define BV_EMI_CTRL_AXI_DEPTH__THREE                0x2
#define BV_EMI_CTRL_AXI_DEPTH__FOUR                 0x3
#define BF_EMI_CTRL_AXI_DEPTH(v)                    (((v) & 0x3) << 26)
#define BFM_EMI_CTRL_AXI_DEPTH(v)                   BM_EMI_CTRL_AXI_DEPTH
#define BF_EMI_CTRL_AXI_DEPTH_V(e)                  BF_EMI_CTRL_AXI_DEPTH(BV_EMI_CTRL_AXI_DEPTH__##e)
#define BFM_EMI_CTRL_AXI_DEPTH_V(v)                 BM_EMI_CTRL_AXI_DEPTH
#define BP_EMI_CTRL_DLL_SHIFT_RESET                 25
#define BM_EMI_CTRL_DLL_SHIFT_RESET                 0x2000000
#define BF_EMI_CTRL_DLL_SHIFT_RESET(v)              (((v) & 0x1) << 25)
#define BFM_EMI_CTRL_DLL_SHIFT_RESET(v)             BM_EMI_CTRL_DLL_SHIFT_RESET
#define BF_EMI_CTRL_DLL_SHIFT_RESET_V(e)            BF_EMI_CTRL_DLL_SHIFT_RESET(BV_EMI_CTRL_DLL_SHIFT_RESET__##e)
#define BFM_EMI_CTRL_DLL_SHIFT_RESET_V(v)           BM_EMI_CTRL_DLL_SHIFT_RESET
#define BP_EMI_CTRL_DLL_RESET                       24
#define BM_EMI_CTRL_DLL_RESET                       0x1000000
#define BF_EMI_CTRL_DLL_RESET(v)                    (((v) & 0x1) << 24)
#define BFM_EMI_CTRL_DLL_RESET(v)                   BM_EMI_CTRL_DLL_RESET
#define BF_EMI_CTRL_DLL_RESET_V(e)                  BF_EMI_CTRL_DLL_RESET(BV_EMI_CTRL_DLL_RESET__##e)
#define BFM_EMI_CTRL_DLL_RESET_V(v)                 BM_EMI_CTRL_DLL_RESET
#define BP_EMI_CTRL_ARB_MODE                        22
#define BM_EMI_CTRL_ARB_MODE                        0xc00000
#define BV_EMI_CTRL_ARB_MODE__TIMESTAMP             0x0
#define BV_EMI_CTRL_ARB_MODE__WRITE_HYBRID          0x1
#define BV_EMI_CTRL_ARB_MODE__PORT_PRIORITY         0x2
#define BF_EMI_CTRL_ARB_MODE(v)                     (((v) & 0x3) << 22)
#define BFM_EMI_CTRL_ARB_MODE(v)                    BM_EMI_CTRL_ARB_MODE
#define BF_EMI_CTRL_ARB_MODE_V(e)                   BF_EMI_CTRL_ARB_MODE(BV_EMI_CTRL_ARB_MODE__##e)
#define BFM_EMI_CTRL_ARB_MODE_V(v)                  BM_EMI_CTRL_ARB_MODE
#define BP_EMI_CTRL_RSVD3                           21
#define BM_EMI_CTRL_RSVD3                           0x200000
#define BF_EMI_CTRL_RSVD3(v)                        (((v) & 0x1) << 21)
#define BFM_EMI_CTRL_RSVD3(v)                       BM_EMI_CTRL_RSVD3
#define BF_EMI_CTRL_RSVD3_V(e)                      BF_EMI_CTRL_RSVD3(BV_EMI_CTRL_RSVD3__##e)
#define BFM_EMI_CTRL_RSVD3_V(v)                     BM_EMI_CTRL_RSVD3
#define BP_EMI_CTRL_PORT_PRIORITY_ORDER             16
#define BM_EMI_CTRL_PORT_PRIORITY_ORDER             0x1f0000
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0123   0x0
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0312   0x1
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0231   0x2
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0321   0x3
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0213   0x4
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0132   0x5
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1023   0x6
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1302   0x7
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1230   0x8
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1320   0x9
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1203   0xa
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1032   0xb
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2013   0xc
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2301   0xd
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2130   0xe
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2310   0xf
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2103   0x10
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2031   0x11
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3012   0x12
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3201   0x13
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3120   0x14
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3210   0x15
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3102   0x16
#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3021   0x17
#define BF_EMI_CTRL_PORT_PRIORITY_ORDER(v)          (((v) & 0x1f) << 16)
#define BFM_EMI_CTRL_PORT_PRIORITY_ORDER(v)         BM_EMI_CTRL_PORT_PRIORITY_ORDER
#define BF_EMI_CTRL_PORT_PRIORITY_ORDER_V(e)        BF_EMI_CTRL_PORT_PRIORITY_ORDER(BV_EMI_CTRL_PORT_PRIORITY_ORDER__##e)
#define BFM_EMI_CTRL_PORT_PRIORITY_ORDER_V(v)       BM_EMI_CTRL_PORT_PRIORITY_ORDER
#define BP_EMI_CTRL_RSVD2                           15
#define BM_EMI_CTRL_RSVD2                           0x8000
#define BF_EMI_CTRL_RSVD2(v)                        (((v) & 0x1) << 15)
#define BFM_EMI_CTRL_RSVD2(v)                       BM_EMI_CTRL_RSVD2
#define BF_EMI_CTRL_RSVD2_V(e)                      BF_EMI_CTRL_RSVD2(BV_EMI_CTRL_RSVD2__##e)
#define BFM_EMI_CTRL_RSVD2_V(v)                     BM_EMI_CTRL_RSVD2
#define BP_EMI_CTRL_PRIORITY_WRITE_ITER             12
#define BM_EMI_CTRL_PRIORITY_WRITE_ITER             0x7000
#define BF_EMI_CTRL_PRIORITY_WRITE_ITER(v)          (((v) & 0x7) << 12)
#define BFM_EMI_CTRL_PRIORITY_WRITE_ITER(v)         BM_EMI_CTRL_PRIORITY_WRITE_ITER
#define BF_EMI_CTRL_PRIORITY_WRITE_ITER_V(e)        BF_EMI_CTRL_PRIORITY_WRITE_ITER(BV_EMI_CTRL_PRIORITY_WRITE_ITER__##e)
#define BFM_EMI_CTRL_PRIORITY_WRITE_ITER_V(v)       BM_EMI_CTRL_PRIORITY_WRITE_ITER
#define BP_EMI_CTRL_RSVD1                           11
#define BM_EMI_CTRL_RSVD1                           0x800
#define BF_EMI_CTRL_RSVD1(v)                        (((v) & 0x1) << 11)
#define BFM_EMI_CTRL_RSVD1(v)                       BM_EMI_CTRL_RSVD1
#define BF_EMI_CTRL_RSVD1_V(e)                      BF_EMI_CTRL_RSVD1(BV_EMI_CTRL_RSVD1__##e)
#define BFM_EMI_CTRL_RSVD1_V(v)                     BM_EMI_CTRL_RSVD1
#define BP_EMI_CTRL_HIGH_PRIORITY_WRITE             8
#define BM_EMI_CTRL_HIGH_PRIORITY_WRITE             0x700
#define BF_EMI_CTRL_HIGH_PRIORITY_WRITE(v)          (((v) & 0x7) << 8)
#define BFM_EMI_CTRL_HIGH_PRIORITY_WRITE(v)         BM_EMI_CTRL_HIGH_PRIORITY_WRITE
#define BF_EMI_CTRL_HIGH_PRIORITY_WRITE_V(e)        BF_EMI_CTRL_HIGH_PRIORITY_WRITE(BV_EMI_CTRL_HIGH_PRIORITY_WRITE__##e)
#define BFM_EMI_CTRL_HIGH_PRIORITY_WRITE_V(v)       BM_EMI_CTRL_HIGH_PRIORITY_WRITE
#define BP_EMI_CTRL_RSVD0                           7
#define BM_EMI_CTRL_RSVD0                           0x80
#define BF_EMI_CTRL_RSVD0(v)                        (((v) & 0x1) << 7)
#define BFM_EMI_CTRL_RSVD0(v)                       BM_EMI_CTRL_RSVD0
#define BF_EMI_CTRL_RSVD0_V(e)                      BF_EMI_CTRL_RSVD0(BV_EMI_CTRL_RSVD0__##e)
#define BFM_EMI_CTRL_RSVD0_V(v)                     BM_EMI_CTRL_RSVD0
#define BP_EMI_CTRL_MEM_WIDTH                       6
#define BM_EMI_CTRL_MEM_WIDTH                       0x40
#define BF_EMI_CTRL_MEM_WIDTH(v)                    (((v) & 0x1) << 6)
#define BFM_EMI_CTRL_MEM_WIDTH(v)                   BM_EMI_CTRL_MEM_WIDTH
#define BF_EMI_CTRL_MEM_WIDTH_V(e)                  BF_EMI_CTRL_MEM_WIDTH(BV_EMI_CTRL_MEM_WIDTH__##e)
#define BFM_EMI_CTRL_MEM_WIDTH_V(v)                 BM_EMI_CTRL_MEM_WIDTH
#define BP_EMI_CTRL_WRITE_PROTECT                   5
#define BM_EMI_CTRL_WRITE_PROTECT                   0x20
#define BF_EMI_CTRL_WRITE_PROTECT(v)                (((v) & 0x1) << 5)
#define BFM_EMI_CTRL_WRITE_PROTECT(v)               BM_EMI_CTRL_WRITE_PROTECT
#define BF_EMI_CTRL_WRITE_PROTECT_V(e)              BF_EMI_CTRL_WRITE_PROTECT(BV_EMI_CTRL_WRITE_PROTECT__##e)
#define BFM_EMI_CTRL_WRITE_PROTECT_V(v)             BM_EMI_CTRL_WRITE_PROTECT
#define BP_EMI_CTRL_RESET_OUT                       4
#define BM_EMI_CTRL_RESET_OUT                       0x10
#define BF_EMI_CTRL_RESET_OUT(v)                    (((v) & 0x1) << 4)
#define BFM_EMI_CTRL_RESET_OUT(v)                   BM_EMI_CTRL_RESET_OUT
#define BF_EMI_CTRL_RESET_OUT_V(e)                  BF_EMI_CTRL_RESET_OUT(BV_EMI_CTRL_RESET_OUT__##e)
#define BFM_EMI_CTRL_RESET_OUT_V(v)                 BM_EMI_CTRL_RESET_OUT
#define BP_EMI_CTRL_CE_SELECT                       0
#define BM_EMI_CTRL_CE_SELECT                       0xf
#define BV_EMI_CTRL_CE_SELECT__NONE                 0x0
#define BV_EMI_CTRL_CE_SELECT__CE0                  0x1
#define BV_EMI_CTRL_CE_SELECT__CE1                  0x2
#define BV_EMI_CTRL_CE_SELECT__CE2                  0x4
#define BV_EMI_CTRL_CE_SELECT__CE3                  0x8
#define BF_EMI_CTRL_CE_SELECT(v)                    (((v) & 0xf) << 0)
#define BFM_EMI_CTRL_CE_SELECT(v)                   BM_EMI_CTRL_CE_SELECT
#define BF_EMI_CTRL_CE_SELECT_V(e)                  BF_EMI_CTRL_CE_SELECT(BV_EMI_CTRL_CE_SELECT__##e)
#define BFM_EMI_CTRL_CE_SELECT_V(v)                 BM_EMI_CTRL_CE_SELECT

#define HW_EMI_STAT                             HW(EMI_STAT)
#define HWA_EMI_STAT                            (0x80020000 + 0x10)
#define HWT_EMI_STAT                            HWIO_32_RW
#define HWN_EMI_STAT                            EMI_STAT
#define HWI_EMI_STAT                            
#define BP_EMI_STAT_DRAM_PRESENT                31
#define BM_EMI_STAT_DRAM_PRESENT                0x80000000
#define BF_EMI_STAT_DRAM_PRESENT(v)             (((v) & 0x1) << 31)
#define BFM_EMI_STAT_DRAM_PRESENT(v)            BM_EMI_STAT_DRAM_PRESENT
#define BF_EMI_STAT_DRAM_PRESENT_V(e)           BF_EMI_STAT_DRAM_PRESENT(BV_EMI_STAT_DRAM_PRESENT__##e)
#define BFM_EMI_STAT_DRAM_PRESENT_V(v)          BM_EMI_STAT_DRAM_PRESENT
#define BP_EMI_STAT_NOR_PRESENT                 30
#define BM_EMI_STAT_NOR_PRESENT                 0x40000000
#define BF_EMI_STAT_NOR_PRESENT(v)              (((v) & 0x1) << 30)
#define BFM_EMI_STAT_NOR_PRESENT(v)             BM_EMI_STAT_NOR_PRESENT
#define BF_EMI_STAT_NOR_PRESENT_V(e)            BF_EMI_STAT_NOR_PRESENT(BV_EMI_STAT_NOR_PRESENT__##e)
#define BFM_EMI_STAT_NOR_PRESENT_V(v)           BM_EMI_STAT_NOR_PRESENT
#define BP_EMI_STAT_LARGE_DRAM_ENABLED          29
#define BM_EMI_STAT_LARGE_DRAM_ENABLED          0x20000000
#define BF_EMI_STAT_LARGE_DRAM_ENABLED(v)       (((v) & 0x1) << 29)
#define BFM_EMI_STAT_LARGE_DRAM_ENABLED(v)      BM_EMI_STAT_LARGE_DRAM_ENABLED
#define BF_EMI_STAT_LARGE_DRAM_ENABLED_V(e)     BF_EMI_STAT_LARGE_DRAM_ENABLED(BV_EMI_STAT_LARGE_DRAM_ENABLED__##e)
#define BFM_EMI_STAT_LARGE_DRAM_ENABLED_V(v)    BM_EMI_STAT_LARGE_DRAM_ENABLED
#define BP_EMI_STAT_RSVD0                       2
#define BM_EMI_STAT_RSVD0                       0x1ffffffc
#define BF_EMI_STAT_RSVD0(v)                    (((v) & 0x7ffffff) << 2)
#define BFM_EMI_STAT_RSVD0(v)                   BM_EMI_STAT_RSVD0
#define BF_EMI_STAT_RSVD0_V(e)                  BF_EMI_STAT_RSVD0(BV_EMI_STAT_RSVD0__##e)
#define BFM_EMI_STAT_RSVD0_V(v)                 BM_EMI_STAT_RSVD0
#define BP_EMI_STAT_DRAM_HALTED                 1
#define BM_EMI_STAT_DRAM_HALTED                 0x2
#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED     0x0
#define BV_EMI_STAT_DRAM_HALTED__HALTED         0x1
#define BF_EMI_STAT_DRAM_HALTED(v)              (((v) & 0x1) << 1)
#define BFM_EMI_STAT_DRAM_HALTED(v)             BM_EMI_STAT_DRAM_HALTED
#define BF_EMI_STAT_DRAM_HALTED_V(e)            BF_EMI_STAT_DRAM_HALTED(BV_EMI_STAT_DRAM_HALTED__##e)
#define BFM_EMI_STAT_DRAM_HALTED_V(v)           BM_EMI_STAT_DRAM_HALTED
#define BP_EMI_STAT_NOR_BUSY                    0
#define BM_EMI_STAT_NOR_BUSY                    0x1
#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY          0x0
#define BV_EMI_STAT_NOR_BUSY__BUSY              0x1
#define BF_EMI_STAT_NOR_BUSY(v)                 (((v) & 0x1) << 0)
#define BFM_EMI_STAT_NOR_BUSY(v)                BM_EMI_STAT_NOR_BUSY
#define BF_EMI_STAT_NOR_BUSY_V(e)               BF_EMI_STAT_NOR_BUSY(BV_EMI_STAT_NOR_BUSY__##e)
#define BFM_EMI_STAT_NOR_BUSY_V(v)              BM_EMI_STAT_NOR_BUSY

#define HW_EMI_TIME             HW(EMI_TIME)
#define HWA_EMI_TIME            (0x80020000 + 0x20)
#define HWT_EMI_TIME            HWIO_32_RW
#define HWN_EMI_TIME            EMI_TIME
#define HWI_EMI_TIME            
#define HW_EMI_TIME_SET         HW(EMI_TIME_SET)
#define HWA_EMI_TIME_SET        (HWA_EMI_TIME + 0x4)
#define HWT_EMI_TIME_SET        HWIO_32_WO
#define HWN_EMI_TIME_SET        EMI_TIME
#define HWI_EMI_TIME_SET        
#define HW_EMI_TIME_CLR         HW(EMI_TIME_CLR)
#define HWA_EMI_TIME_CLR        (HWA_EMI_TIME + 0x8)
#define HWT_EMI_TIME_CLR        HWIO_32_WO
#define HWN_EMI_TIME_CLR        EMI_TIME
#define HWI_EMI_TIME_CLR        
#define HW_EMI_TIME_TOG         HW(EMI_TIME_TOG)
#define HWA_EMI_TIME_TOG        (HWA_EMI_TIME + 0xc)
#define HWT_EMI_TIME_TOG        HWIO_32_WO
#define HWN_EMI_TIME_TOG        EMI_TIME
#define HWI_EMI_TIME_TOG        
#define BP_EMI_TIME_RSVD4       28
#define BM_EMI_TIME_RSVD4       0xf0000000
#define BF_EMI_TIME_RSVD4(v)    (((v) & 0xf) << 28)
#define BFM_EMI_TIME_RSVD4(v)   BM_EMI_TIME_RSVD4
#define BF_EMI_TIME_RSVD4_V(e)  BF_EMI_TIME_RSVD4(BV_EMI_TIME_RSVD4__##e)
#define BFM_EMI_TIME_RSVD4_V(v) BM_EMI_TIME_RSVD4
#define BP_EMI_TIME_THZ         24
#define BM_EMI_TIME_THZ         0xf000000
#define BF_EMI_TIME_THZ(v)      (((v) & 0xf) << 24)
#define BFM_EMI_TIME_THZ(v)     BM_EMI_TIME_THZ
#define BF_EMI_TIME_THZ_V(e)    BF_EMI_TIME_THZ(BV_EMI_TIME_THZ__##e)
#define BFM_EMI_TIME_THZ_V(v)   BM_EMI_TIME_THZ
#define BP_EMI_TIME_RSVD2       20
#define BM_EMI_TIME_RSVD2       0xf00000
#define BF_EMI_TIME_RSVD2(v)    (((v) & 0xf) << 20)
#define BFM_EMI_TIME_RSVD2(v)   BM_EMI_TIME_RSVD2
#define BF_EMI_TIME_RSVD2_V(e)  BF_EMI_TIME_RSVD2(BV_EMI_TIME_RSVD2__##e)
#define BFM_EMI_TIME_RSVD2_V(v) BM_EMI_TIME_RSVD2
#define BP_EMI_TIME_TDH         16
#define BM_EMI_TIME_TDH         0xf0000
#define BF_EMI_TIME_TDH(v)      (((v) & 0xf) << 16)
#define BFM_EMI_TIME_TDH(v)     BM_EMI_TIME_TDH
#define BF_EMI_TIME_TDH_V(e)    BF_EMI_TIME_TDH(BV_EMI_TIME_TDH__##e)
#define BFM_EMI_TIME_TDH_V(v)   BM_EMI_TIME_TDH
#define BP_EMI_TIME_RSVD1       13
#define BM_EMI_TIME_RSVD1       0xe000
#define BF_EMI_TIME_RSVD1(v)    (((v) & 0x7) << 13)
#define BFM_EMI_TIME_RSVD1(v)   BM_EMI_TIME_RSVD1
#define BF_EMI_TIME_RSVD1_V(e)  BF_EMI_TIME_RSVD1(BV_EMI_TIME_RSVD1__##e)
#define BFM_EMI_TIME_RSVD1_V(v) BM_EMI_TIME_RSVD1
#define BP_EMI_TIME_TDS         8
#define BM_EMI_TIME_TDS         0x1f00
#define BF_EMI_TIME_TDS(v)      (((v) & 0x1f) << 8)
#define BFM_EMI_TIME_TDS(v)     BM_EMI_TIME_TDS
#define BF_EMI_TIME_TDS_V(e)    BF_EMI_TIME_TDS(BV_EMI_TIME_TDS__##e)
#define BFM_EMI_TIME_TDS_V(v)   BM_EMI_TIME_TDS
#define BP_EMI_TIME_RSVD0       4
#define BM_EMI_TIME_RSVD0       0xf0
#define BF_EMI_TIME_RSVD0(v)    (((v) & 0xf) << 4)
#define BFM_EMI_TIME_RSVD0(v)   BM_EMI_TIME_RSVD0
#define BF_EMI_TIME_RSVD0_V(e)  BF_EMI_TIME_RSVD0(BV_EMI_TIME_RSVD0__##e)
#define BFM_EMI_TIME_RSVD0_V(v) BM_EMI_TIME_RSVD0
#define BP_EMI_TIME_TAS         0
#define BM_EMI_TIME_TAS         0xf
#define BF_EMI_TIME_TAS(v)      (((v) & 0xf) << 0)
#define BFM_EMI_TIME_TAS(v)     BM_EMI_TIME_TAS
#define BF_EMI_TIME_TAS_V(e)    BF_EMI_TIME_TAS(BV_EMI_TIME_TAS__##e)
#define BFM_EMI_TIME_TAS_V(v)   BM_EMI_TIME_TAS

#define HW_EMI_DDR_TEST_MODE_CSR                HW(EMI_DDR_TEST_MODE_CSR)
#define HWA_EMI_DDR_TEST_MODE_CSR               (0x80020000 + 0x30)
#define HWT_EMI_DDR_TEST_MODE_CSR               HWIO_32_RW
#define HWN_EMI_DDR_TEST_MODE_CSR               EMI_DDR_TEST_MODE_CSR
#define HWI_EMI_DDR_TEST_MODE_CSR               
#define HW_EMI_DDR_TEST_MODE_CSR_SET            HW(EMI_DDR_TEST_MODE_CSR_SET)
#define HWA_EMI_DDR_TEST_MODE_CSR_SET           (HWA_EMI_DDR_TEST_MODE_CSR + 0x4)
#define HWT_EMI_DDR_TEST_MODE_CSR_SET           HWIO_32_WO
#define HWN_EMI_DDR_TEST_MODE_CSR_SET           EMI_DDR_TEST_MODE_CSR
#define HWI_EMI_DDR_TEST_MODE_CSR_SET           
#define HW_EMI_DDR_TEST_MODE_CSR_CLR            HW(EMI_DDR_TEST_MODE_CSR_CLR)
#define HWA_EMI_DDR_TEST_MODE_CSR_CLR           (HWA_EMI_DDR_TEST_MODE_CSR + 0x8)
#define HWT_EMI_DDR_TEST_MODE_CSR_CLR           HWIO_32_WO
#define HWN_EMI_DDR_TEST_MODE_CSR_CLR           EMI_DDR_TEST_MODE_CSR
#define HWI_EMI_DDR_TEST_MODE_CSR_CLR           
#define HW_EMI_DDR_TEST_MODE_CSR_TOG            HW(EMI_DDR_TEST_MODE_CSR_TOG)
#define HWA_EMI_DDR_TEST_MODE_CSR_TOG           (HWA_EMI_DDR_TEST_MODE_CSR + 0xc)
#define HWT_EMI_DDR_TEST_MODE_CSR_TOG           HWIO_32_WO
#define HWN_EMI_DDR_TEST_MODE_CSR_TOG           EMI_DDR_TEST_MODE_CSR
#define HWI_EMI_DDR_TEST_MODE_CSR_TOG           
#define BP_EMI_DDR_TEST_MODE_CSR_RSVD1          2
#define BM_EMI_DDR_TEST_MODE_CSR_RSVD1          0xfffffffc
#define BF_EMI_DDR_TEST_MODE_CSR_RSVD1(v)       (((v) & 0x3fffffff) << 2)
#define BFM_EMI_DDR_TEST_MODE_CSR_RSVD1(v)      BM_EMI_DDR_TEST_MODE_CSR_RSVD1
#define BF_EMI_DDR_TEST_MODE_CSR_RSVD1_V(e)     BF_EMI_DDR_TEST_MODE_CSR_RSVD1(BV_EMI_DDR_TEST_MODE_CSR_RSVD1__##e)
#define BFM_EMI_DDR_TEST_MODE_CSR_RSVD1_V(v)    BM_EMI_DDR_TEST_MODE_CSR_RSVD1
#define BP_EMI_DDR_TEST_MODE_CSR_DONE           1
#define BM_EMI_DDR_TEST_MODE_CSR_DONE           0x2
#define BF_EMI_DDR_TEST_MODE_CSR_DONE(v)        (((v) & 0x1) << 1)
#define BFM_EMI_DDR_TEST_MODE_CSR_DONE(v)       BM_EMI_DDR_TEST_MODE_CSR_DONE
#define BF_EMI_DDR_TEST_MODE_CSR_DONE_V(e)      BF_EMI_DDR_TEST_MODE_CSR_DONE(BV_EMI_DDR_TEST_MODE_CSR_DONE__##e)
#define BFM_EMI_DDR_TEST_MODE_CSR_DONE_V(v)     BM_EMI_DDR_TEST_MODE_CSR_DONE
#define BP_EMI_DDR_TEST_MODE_CSR_START          0
#define BM_EMI_DDR_TEST_MODE_CSR_START          0x1
#define BF_EMI_DDR_TEST_MODE_CSR_START(v)       (((v) & 0x1) << 0)
#define BFM_EMI_DDR_TEST_MODE_CSR_START(v)      BM_EMI_DDR_TEST_MODE_CSR_START
#define BF_EMI_DDR_TEST_MODE_CSR_START_V(e)     BF_EMI_DDR_TEST_MODE_CSR_START(BV_EMI_DDR_TEST_MODE_CSR_START__##e)
#define BFM_EMI_DDR_TEST_MODE_CSR_START_V(v)    BM_EMI_DDR_TEST_MODE_CSR_START

#define HW_EMI_DEBUG                    HW(EMI_DEBUG)
#define HWA_EMI_DEBUG                   (0x80020000 + 0x80)
#define HWT_EMI_DEBUG                   HWIO_32_RW
#define HWN_EMI_DEBUG                   EMI_DEBUG
#define HWI_EMI_DEBUG                   
#define BP_EMI_DEBUG_RSVD1              4
#define BM_EMI_DEBUG_RSVD1              0xfffffff0
#define BF_EMI_DEBUG_RSVD1(v)           (((v) & 0xfffffff) << 4)
#define BFM_EMI_DEBUG_RSVD1(v)          BM_EMI_DEBUG_RSVD1
#define BF_EMI_DEBUG_RSVD1_V(e)         BF_EMI_DEBUG_RSVD1(BV_EMI_DEBUG_RSVD1__##e)
#define BFM_EMI_DEBUG_RSVD1_V(v)        BM_EMI_DEBUG_RSVD1
#define BP_EMI_DEBUG_NOR_STATE          0
#define BM_EMI_DEBUG_NOR_STATE          0xf
#define BF_EMI_DEBUG_NOR_STATE(v)       (((v) & 0xf) << 0)
#define BFM_EMI_DEBUG_NOR_STATE(v)      BM_EMI_DEBUG_NOR_STATE
#define BF_EMI_DEBUG_NOR_STATE_V(e)     BF_EMI_DEBUG_NOR_STATE(BV_EMI_DEBUG_NOR_STATE__##e)
#define BFM_EMI_DEBUG_NOR_STATE_V(v)    BM_EMI_DEBUG_NOR_STATE

#define HW_EMI_DDR_TEST_MODE_STATUS0                HW(EMI_DDR_TEST_MODE_STATUS0)
#define HWA_EMI_DDR_TEST_MODE_STATUS0               (0x80020000 + 0x90)
#define HWT_EMI_DDR_TEST_MODE_STATUS0               HWIO_32_RW
#define HWN_EMI_DDR_TEST_MODE_STATUS0               EMI_DDR_TEST_MODE_STATUS0
#define HWI_EMI_DDR_TEST_MODE_STATUS0               
#define BP_EMI_DDR_TEST_MODE_STATUS0_RSVD1          13
#define BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1          0xffffe000
#define BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1(v)       (((v) & 0x7ffff) << 13)
#define BFM_EMI_DDR_TEST_MODE_STATUS0_RSVD1(v)      BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1
#define BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1_V(e)     BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1(BV_EMI_DDR_TEST_MODE_STATUS0_RSVD1__##e)
#define BFM_EMI_DDR_TEST_MODE_STATUS0_RSVD1_V(v)    BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1
#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0          0
#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0          0x1fff
#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v)       (((v) & 0x1fff) << 0)
#define BFM_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v)      BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0
#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0_V(e)     BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(BV_EMI_DDR_TEST_MODE_STATUS0_ADDR0__##e)
#define BFM_EMI_DDR_TEST_MODE_STATUS0_ADDR0_V(v)    BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0

#define HW_EMI_DDR_TEST_MODE_STATUS1                HW(EMI_DDR_TEST_MODE_STATUS1)
#define HWA_EMI_DDR_TEST_MODE_STATUS1               (0x80020000 + 0xa0)
#define HWT_EMI_DDR_TEST_MODE_STATUS1               HWIO_32_RW
#define HWN_EMI_DDR_TEST_MODE_STATUS1               EMI_DDR_TEST_MODE_STATUS1
#define HWI_EMI_DDR_TEST_MODE_STATUS1               
#define BP_EMI_DDR_TEST_MODE_STATUS1_RSVD1          13
#define BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1          0xffffe000
#define BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1(v)       (((v) & 0x7ffff) << 13)
#define BFM_EMI_DDR_TEST_MODE_STATUS1_RSVD1(v)      BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1
#define BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1_V(e)     BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1(BV_EMI_DDR_TEST_MODE_STATUS1_RSVD1__##e)
#define BFM_EMI_DDR_TEST_MODE_STATUS1_RSVD1_V(v)    BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1
#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1          0
#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1          0x1fff
#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v)       (((v) & 0x1fff) << 0)
#define BFM_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v)      BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1
#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1_V(e)     BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(BV_EMI_DDR_TEST_MODE_STATUS1_ADDR1__##e)
#define BFM_EMI_DDR_TEST_MODE_STATUS1_ADDR1_V(v)    BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1

#define HW_EMI_DDR_TEST_MODE_STATUS2                HW(EMI_DDR_TEST_MODE_STATUS2)
#define HWA_EMI_DDR_TEST_MODE_STATUS2               (0x80020000 + 0xb0)
#define HWT_EMI_DDR_TEST_MODE_STATUS2               HWIO_32_RW
#define HWN_EMI_DDR_TEST_MODE_STATUS2               EMI_DDR_TEST_MODE_STATUS2
#define HWI_EMI_DDR_TEST_MODE_STATUS2               
#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0          0
#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0          0xffffffff
#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v)       (((v) & 0xffffffff) << 0)
#define BFM_EMI_DDR_TEST_MODE_STATUS2_DATA0(v)      BM_EMI_DDR_TEST_MODE_STATUS2_DATA0
#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0_V(e)     BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(BV_EMI_DDR_TEST_MODE_STATUS2_DATA0__##e)
#define BFM_EMI_DDR_TEST_MODE_STATUS2_DATA0_V(v)    BM_EMI_DDR_TEST_MODE_STATUS2_DATA0

#define HW_EMI_DDR_TEST_MODE_STATUS3                HW(EMI_DDR_TEST_MODE_STATUS3)
#define HWA_EMI_DDR_TEST_MODE_STATUS3               (0x80020000 + 0xc0)
#define HWT_EMI_DDR_TEST_MODE_STATUS3               HWIO_32_RW
#define HWN_EMI_DDR_TEST_MODE_STATUS3               EMI_DDR_TEST_MODE_STATUS3
#define HWI_EMI_DDR_TEST_MODE_STATUS3               
#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1          0
#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1          0xffffffff
#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v)       (((v) & 0xffffffff) << 0)
#define BFM_EMI_DDR_TEST_MODE_STATUS3_DATA1(v)      BM_EMI_DDR_TEST_MODE_STATUS3_DATA1
#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1_V(e)     BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(BV_EMI_DDR_TEST_MODE_STATUS3_DATA1__##e)
#define BFM_EMI_DDR_TEST_MODE_STATUS3_DATA1_V(v)    BM_EMI_DDR_TEST_MODE_STATUS3_DATA1

#define HW_EMI_VERSION              HW(EMI_VERSION)
#define HWA_EMI_VERSION             (0x80020000 + 0xf0)
#define HWT_EMI_VERSION             HWIO_32_RW
#define HWN_EMI_VERSION             EMI_VERSION
#define HWI_EMI_VERSION             
#define BP_EMI_VERSION_MAJOR        24
#define BM_EMI_VERSION_MAJOR        0xff000000
#define BF_EMI_VERSION_MAJOR(v)     (((v) & 0xff) << 24)
#define BFM_EMI_VERSION_MAJOR(v)    BM_EMI_VERSION_MAJOR
#define BF_EMI_VERSION_MAJOR_V(e)   BF_EMI_VERSION_MAJOR(BV_EMI_VERSION_MAJOR__##e)
#define BFM_EMI_VERSION_MAJOR_V(v)  BM_EMI_VERSION_MAJOR
#define BP_EMI_VERSION_MINOR        16
#define BM_EMI_VERSION_MINOR        0xff0000
#define BF_EMI_VERSION_MINOR(v)     (((v) & 0xff) << 16)
#define BFM_EMI_VERSION_MINOR(v)    BM_EMI_VERSION_MINOR
#define BF_EMI_VERSION_MINOR_V(e)   BF_EMI_VERSION_MINOR(BV_EMI_VERSION_MINOR__##e)
#define BFM_EMI_VERSION_MINOR_V(v)  BM_EMI_VERSION_MINOR
#define BP_EMI_VERSION_STEP         0
#define BM_EMI_VERSION_STEP         0xffff
#define BF_EMI_VERSION_STEP(v)      (((v) & 0xffff) << 0)
#define BFM_EMI_VERSION_STEP(v)     BM_EMI_VERSION_STEP
#define BF_EMI_VERSION_STEP_V(e)    BF_EMI_VERSION_STEP(BV_EMI_VERSION_STEP__##e)
#define BFM_EMI_VERSION_STEP_V(v)   BM_EMI_VERSION_STEP

#endif /* __HEADERGEN_IMX233_EMI_H__*/
