/*************************************************************************** * __________ __ ___. * Open \______ \ ____ ____ | | _\_ |__ _______ ___ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. * headergen version: 3.0.0 * stmp3600 version: 2.4.0 * stmp3600 authors: Amaury Pouly * * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * ****************************************************************************/ #ifndef __HEADERGEN_STMP3600_DIGCTL_H__ #define __HEADERGEN_STMP3600_DIGCTL_H__ #define HW_DIGCTL_CTRL HW(DIGCTL_CTRL) #define HWA_DIGCTL_CTRL (0x8001c000 + 0x0) #define HWT_DIGCTL_CTRL HWIO_32_RW #define HWN_DIGCTL_CTRL DIGCTL_CTRL #define HWI_DIGCTL_CTRL #define HW_DIGCTL_CTRL_SET HW(DIGCTL_CTRL_SET) #define HWA_DIGCTL_CTRL_SET (HWA_DIGCTL_CTRL + 0x4) #define HWT_DIGCTL_CTRL_SET HWIO_32_WO #define HWN_DIGCTL_CTRL_SET DIGCTL_CTRL #define HWI_DIGCTL_CTRL_SET #define HW_DIGCTL_CTRL_CLR HW(DIGCTL_CTRL_CLR) #define HWA_DIGCTL_CTRL_CLR (HWA_DIGCTL_CTRL + 0x8) #define HWT_DIGCTL_CTRL_CLR HWIO_32_WO #define HWN_DIGCTL_CTRL_CLR DIGCTL_CTRL #define HWI_DIGCTL_CTRL_CLR #define HW_DIGCTL_CTRL_TOG HW(DIGCTL_CTRL_TOG) #define HWA_DIGCTL_CTRL_TOG (HWA_DIGCTL_CTRL + 0xc) #define HWT_DIGCTL_CTRL_TOG HWIO_32_WO #define HWN_DIGCTL_CTRL_TOG DIGCTL_CTRL #define HWI_DIGCTL_CTRL_TOG #define BP_DIGCTL_CTRL_MASTER_SELECT 24 #define BM_DIGCTL_CTRL_MASTER_SELECT 0x1f000000 #define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_I 0x1 #define BV_DIGCTL_CTRL_MASTER_SELECT__ARM_D 0x2 #define BV_DIGCTL_CTRL_MASTER_SELECT__USB 0x4 #define BV_DIGCTL_CTRL_MASTER_SELECT__APBH 0x8 #define BV_DIGCTL_CTRL_MASTER_SELECT__APBX 0x10 #define BF_DIGCTL_CTRL_MASTER_SELECT(v) (((v) & 0x1f) << 24) #define BFM_DIGCTL_CTRL_MASTER_SELECT(v) BM_DIGCTL_CTRL_MASTER_SELECT #define BF_DIGCTL_CTRL_MASTER_SELECT_V(e) BF_DIGCTL_CTRL_MASTER_SELECT(BV_DIGCTL_CTRL_MASTER_SELECT__##e) #define BFM_DIGCTL_CTRL_MASTER_SELECT_V(v) BM_DIGCTL_CTRL_MASTER_SELECT #define BP_DIGCTL_CTRL_USB_TESTMODE 20 #define BM_DIGCTL_CTRL_USB_TESTMODE 0x100000 #define BF_DIGCTL_CTRL_USB_TESTMODE(v) (((v) & 0x1) << 20) #define BFM_DIGCTL_CTRL_USB_TESTMODE(v) BM_DIGCTL_CTRL_USB_TESTMODE #define BF_DIGCTL_CTRL_USB_TESTMODE_V(e) BF_DIGCTL_CTRL_USB_TESTMODE(BV_DIGCTL_CTRL_USB_TESTMODE__##e) #define BFM_DIGCTL_CTRL_USB_TESTMODE_V(v) BM_DIGCTL_CTRL_USB_TESTMODE #define BP_DIGCTL_CTRL_ANALOG_TESTMODE 19 #define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x80000 #define BF_DIGCTL_CTRL_ANALOG_TESTMODE(v) (((v) & 0x1) << 19) #define BFM_DIGCTL_CTRL_ANALOG_TESTMODE(v) BM_DIGCTL_CTRL_ANALOG_TESTMODE #define BF_DIGCTL_CTRL_ANALOG_TESTMODE_V(e) BF_DIGCTL_CTRL_ANALOG_TESTMODE(BV_DIGCTL_CTRL_ANALOG_TESTMODE__##e) #define BFM_DIGCTL_CTRL_ANALOG_TESTMODE_V(v) BM_DIGCTL_CTRL_ANALOG_TESTMODE #define BP_DIGCTL_CTRL_DIGITAL_TESTMODE 18 #define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x40000 #define BF_DIGCTL_CTRL_DIGITAL_TESTMODE(v) (((v) & 0x1) << 18) #define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE(v) BM_DIGCTL_CTRL_DIGITAL_TESTMODE #define BF_DIGCTL_CTRL_DIGITAL_TESTMODE_V(e) BF_DIGCTL_CTRL_DIGITAL_TESTMODE(BV_DIGCTL_CTRL_DIGITAL_TESTMODE__##e) #define BFM_DIGCTL_CTRL_DIGITAL_TESTMODE_V(v) BM_DIGCTL_CTRL_DIGITAL_TESTMODE #define BP_DIGCTL_CTRL_UTMI_TESTMODE 17 #define BM_DIGCTL_CTRL_UTMI_TESTMODE 0x20000 #define BF_DIGCTL_CTRL_UTMI_TESTMODE(v) (((v) & 0x1) << 17) #define BFM_DIGCTL_CTRL_UTMI_TESTMODE(v) BM_DIGCTL_CTRL_UTMI_TESTMODE #define BF_DIGCTL_CTRL_UTMI_TESTMODE_V(e) BF_DIGCTL_CTRL_UTMI_TESTMODE(BV_DIGCTL_CTRL_UTMI_TESTMODE__##e) #define BFM_DIGCTL_CTRL_UTMI_TESTMODE_V(v) BM_DIGCTL_CTRL_UTMI_TESTMODE #define BP_DIGCTL_CTRL_UART_LOOPBACK 16 #define BM_DIGCTL_CTRL_UART_LOOPBACK 0x10000 #define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 #define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 #define BF_DIGCTL_CTRL_UART_LOOPBACK(v) (((v) & 0x1) << 16) #define BFM_DIGCTL_CTRL_UART_LOOPBACK(v) BM_DIGCTL_CTRL_UART_LOOPBACK #define BF_DIGCTL_CTRL_UART_LOOPBACK_V(e) BF_DIGCTL_CTRL_UART_LOOPBACK(BV_DIGCTL_CTRL_UART_LOOPBACK__##e) #define BFM_DIGCTL_CTRL_UART_LOOPBACK_V(v) BM_DIGCTL_CTRL_UART_LOOPBACK #define BP_DIGCTL_CTRL_DEBUG_DISABLE 3 #define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x8 #define BF_DIGCTL_CTRL_DEBUG_DISABLE(v) (((v) & 0x1) << 3) #define BFM_DIGCTL_CTRL_DEBUG_DISABLE(v) BM_DIGCTL_CTRL_DEBUG_DISABLE #define BF_DIGCTL_CTRL_DEBUG_DISABLE_V(e) BF_DIGCTL_CTRL_DEBUG_DISABLE(BV_DIGCTL_CTRL_DEBUG_DISABLE__##e) #define BFM_DIGCTL_CTRL_DEBUG_DISABLE_V(v) BM_DIGCTL_CTRL_DEBUG_DISABLE #define BP_DIGCTL_CTRL_USB_CLKGATE 2 #define BM_DIGCTL_CTRL_USB_CLKGATE 0x4 #define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 #define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 #define BF_DIGCTL_CTRL_USB_CLKGATE(v) (((v) & 0x1) << 2) #define BFM_DIGCTL_CTRL_USB_CLKGATE(v) BM_DIGCTL_CTRL_USB_CLKGATE #define BF_DIGCTL_CTRL_USB_CLKGATE_V(e) BF_DIGCTL_CTRL_USB_CLKGATE(BV_DIGCTL_CTRL_USB_CLKGATE__##e) #define BFM_DIGCTL_CTRL_USB_CLKGATE_V(v) BM_DIGCTL_CTRL_USB_CLKGATE #define BP_DIGCTL_CTRL_JTAG_SHIELD 1 #define BM_DIGCTL_CTRL_JTAG_SHIELD 0x2 #define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 #define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 #define BF_DIGCTL_CTRL_JTAG_SHIELD(v) (((v) & 0x1) << 1) #define BFM_DIGCTL_CTRL_JTAG_SHIELD(v) BM_DIGCTL_CTRL_JTAG_SHIELD #define BF_DIGCTL_CTRL_JTAG_SHIELD_V(e) BF_DIGCTL_CTRL_JTAG_SHIELD(BV_DIGCTL_CTRL_JTAG_SHIELD__##e) #define BFM_DIGCTL_CTRL_JTAG_SHIELD_V(v) BM_DIGCTL_CTRL_JTAG_SHIELD #define BP_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0 #define BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE 0x1 #define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__DISABLE 0x0 #define BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__ENABLE 0x1 #define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v) (((v) & 0x1) << 0) #define BFM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(v) BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE #define BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(e) BF_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE(BV_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE__##e) #define BFM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE_V(v) BM_DIGCTL_CTRL_PACKAGE_SENSE_ENABLE #define HW_DIGCTL_STATUS HW(DIGCTL_STATUS) #define HWA_DIGCTL_STATUS (0x8001c000 + 0x10) #define HWT_DIGCTL_STATUS HWIO_32_RW #define HWN_DIGCTL_STATUS DIGCTL_STATUS #define HWI_DIGCTL_STATUS #define BP_DIGCTL_STATUS_ROM_KEYS_PRESENT 31 #define BM_DIGCTL_STATUS_ROM_KEYS_PRESENT 0x80000000 #define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(v) (((v) & 0x1) << 31) #define BFM_DIGCTL_STATUS_ROM_KEYS_PRESENT(v) BM_DIGCTL_STATUS_ROM_KEYS_PRESENT #define BF_DIGCTL_STATUS_ROM_KEYS_PRESENT_V(e) BF_DIGCTL_STATUS_ROM_KEYS_PRESENT(BV_DIGCTL_STATUS_ROM_KEYS_PRESENT__##e) #define BFM_DIGCTL_STATUS_ROM_KEYS_PRESENT_V(v) BM_DIGCTL_STATUS_ROM_KEYS_PRESENT #define BP_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 6 #define BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT 0x40 #define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v) (((v) & 0x1) << 6) #define BFM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(v) BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT #define BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT_V(e) BF_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT(BV_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT__##e) #define BFM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT_V(v) BM_DIGCTL_STATUS_JTAG_SHIELD_DEFAULT #define BP_DIGCTL_STATUS_ROM_SHIELDED 5 #define BM_DIGCTL_STATUS_ROM_SHIELDED 0x20 #define BF_DIGCTL_STATUS_ROM_SHIELDED(v) (((v) & 0x1) << 5) #define BFM_DIGCTL_STATUS_ROM_SHIELDED(v) BM_DIGCTL_STATUS_ROM_SHIELDED #define BF_DIGCTL_STATUS_ROM_SHIELDED_V(e) BF_DIGCTL_STATUS_ROM_SHIELDED(BV_DIGCTL_STATUS_ROM_SHIELDED__##e) #define BFM_DIGCTL_STATUS_ROM_SHIELDED_V(v) BM_DIGCTL_STATUS_ROM_SHIELDED #define BP_DIGCTL_STATUS_JTAG_IN_USE 4 #define BM_DIGCTL_STATUS_JTAG_IN_USE 0x10 #define BF_DIGCTL_STATUS_JTAG_IN_USE(v) (((v) & 0x1) << 4) #define BFM_DIGCTL_STATUS_JTAG_IN_USE(v) BM_DIGCTL_STATUS_JTAG_IN_USE #define BF_DIGCTL_STATUS_JTAG_IN_USE_V(e) BF_DIGCTL_STATUS_JTAG_IN_USE(BV_DIGCTL_STATUS_JTAG_IN_USE__##e) #define BFM_DIGCTL_STATUS_JTAG_IN_USE_V(v) BM_DIGCTL_STATUS_JTAG_IN_USE #define BP_DIGCTL_STATUS_PSWITCH 2 #define BM_DIGCTL_STATUS_PSWITCH 0xc #define BF_DIGCTL_STATUS_PSWITCH(v) (((v) & 0x3) << 2) #define BFM_DIGCTL_STATUS_PSWITCH(v) BM_DIGCTL_STATUS_PSWITCH #define BF_DIGCTL_STATUS_PSWITCH_V(e) BF_DIGCTL_STATUS_PSWITCH(BV_DIGCTL_STATUS_PSWITCH__##e) #define BFM_DIGCTL_STATUS_PSWITCH_V(v) BM_DIGCTL_STATUS_PSWITCH #define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 #define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x2 #define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) (((v) & 0x1) << 1) #define BFM_DIGCTL_STATUS_PACKAGE_TYPE(v) BM_DIGCTL_STATUS_PACKAGE_TYPE #define BF_DIGCTL_STATUS_PACKAGE_TYPE_V(e) BF_DIGCTL_STATUS_PACKAGE_TYPE(BV_DIGCTL_STATUS_PACKAGE_TYPE__##e) #define BFM_DIGCTL_STATUS_PACKAGE_TYPE_V(v) BM_DIGCTL_STATUS_PACKAGE_TYPE #define BP_DIGCTL_STATUS_WRITTEN 0 #define BM_DIGCTL_STATUS_WRITTEN 0x1 #define BF_DIGCTL_STATUS_WRITTEN(v) (((v) & 0x1) << 0) #define BFM_DIGCTL_STATUS_WRITTEN(v) BM_DIGCTL_STATUS_WRITTEN #define BF_DIGCTL_STATUS_WRITTEN_V(e) BF_DIGCTL_STATUS_WRITTEN(BV_DIGCTL_STATUS_WRITTEN__##e) #define BFM_DIGCTL_STATUS_WRITTEN_V(v) BM_DIGCTL_STATUS_WRITTEN #define HW_DIGCTL_HCLKCOUNT HW(DIGCTL_HCLKCOUNT) #define HWA_DIGCTL_HCLKCOUNT (0x8001c000 + 0x20) #define HWT_DIGCTL_HCLKCOUNT HWIO_32_RW #define HWN_DIGCTL_HCLKCOUNT DIGCTL_HCLKCOUNT #define HWI_DIGCTL_HCLKCOUNT #define BP_DIGCTL_HCLKCOUNT_COUNT 0 #define BM_DIGCTL_HCLKCOUNT_COUNT 0xffffffff #define BF_DIGCTL_HCLKCOUNT_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_HCLKCOUNT_COUNT(v) BM_DIGCTL_HCLKCOUNT_COUNT #define BF_DIGCTL_HCLKCOUNT_COUNT_V(e) BF_DIGCTL_HCLKCOUNT_COUNT(BV_DIGCTL_HCLKCOUNT_COUNT__##e) #define BFM_DIGCTL_HCLKCOUNT_COUNT_V(v) BM_DIGCTL_HCLKCOUNT_COUNT #define HW_DIGCTL_RAMCTRL HW(DIGCTL_RAMCTRL) #define HWA_DIGCTL_RAMCTRL (0x8001c000 + 0x30) #define HWT_DIGCTL_RAMCTRL HWIO_32_RW #define HWN_DIGCTL_RAMCTRL DIGCTL_RAMCTRL #define HWI_DIGCTL_RAMCTRL #define HW_DIGCTL_RAMCTRL_SET HW(DIGCTL_RAMCTRL_SET) #define HWA_DIGCTL_RAMCTRL_SET (HWA_DIGCTL_RAMCTRL + 0x4) #define HWT_DIGCTL_RAMCTRL_SET HWIO_32_WO #define HWN_DIGCTL_RAMCTRL_SET DIGCTL_RAMCTRL #define HWI_DIGCTL_RAMCTRL_SET #define HW_DIGCTL_RAMCTRL_CLR HW(DIGCTL_RAMCTRL_CLR) #define HWA_DIGCTL_RAMCTRL_CLR (HWA_DIGCTL_RAMCTRL + 0x8) #define HWT_DIGCTL_RAMCTRL_CLR HWIO_32_WO #define HWN_DIGCTL_RAMCTRL_CLR DIGCTL_RAMCTRL #define HWI_DIGCTL_RAMCTRL_CLR #define HW_DIGCTL_RAMCTRL_TOG HW(DIGCTL_RAMCTRL_TOG) #define HWA_DIGCTL_RAMCTRL_TOG (HWA_DIGCTL_RAMCTRL + 0xc) #define HWT_DIGCTL_RAMCTRL_TOG HWIO_32_WO #define HWN_DIGCTL_RAMCTRL_TOG DIGCTL_RAMCTRL #define HWI_DIGCTL_RAMCTRL_TOG #define BP_DIGCTL_RAMCTRL_TEST_MARGIN 28 #define BM_DIGCTL_RAMCTRL_TEST_MARGIN 0x70000000 #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__NORMAL 0x0 #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL1 0x1 #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL2 0x2 #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL3 0x3 #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL4 0x4 #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL5 0x5 #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL6 0x6 #define BV_DIGCTL_RAMCTRL_TEST_MARGIN__LEVEL7 0x7 #define BF_DIGCTL_RAMCTRL_TEST_MARGIN(v) (((v) & 0x7) << 28) #define BFM_DIGCTL_RAMCTRL_TEST_MARGIN(v) BM_DIGCTL_RAMCTRL_TEST_MARGIN #define BF_DIGCTL_RAMCTRL_TEST_MARGIN_V(e) BF_DIGCTL_RAMCTRL_TEST_MARGIN(BV_DIGCTL_RAMCTRL_TEST_MARGIN__##e) #define BFM_DIGCTL_RAMCTRL_TEST_MARGIN_V(v) BM_DIGCTL_RAMCTRL_TEST_MARGIN #define BP_DIGCTL_RAMCTRL_PWDN_BANKS 24 #define BM_DIGCTL_RAMCTRL_PWDN_BANKS 0xf000000 #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK3 0x8 #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK2 0x4 #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK1 0x2 #define BV_DIGCTL_RAMCTRL_PWDN_BANKS__PWDN_BANK0 0x1 #define BF_DIGCTL_RAMCTRL_PWDN_BANKS(v) (((v) & 0xf) << 24) #define BFM_DIGCTL_RAMCTRL_PWDN_BANKS(v) BM_DIGCTL_RAMCTRL_PWDN_BANKS #define BF_DIGCTL_RAMCTRL_PWDN_BANKS_V(e) BF_DIGCTL_RAMCTRL_PWDN_BANKS(BV_DIGCTL_RAMCTRL_PWDN_BANKS__##e) #define BFM_DIGCTL_RAMCTRL_PWDN_BANKS_V(v) BM_DIGCTL_RAMCTRL_PWDN_BANKS #define BP_DIGCTL_RAMCTRL_TEMP_SENSOR 20 #define BM_DIGCTL_RAMCTRL_TEMP_SENSOR 0x700000 #define BF_DIGCTL_RAMCTRL_TEMP_SENSOR(v) (((v) & 0x7) << 20) #define BFM_DIGCTL_RAMCTRL_TEMP_SENSOR(v) BM_DIGCTL_RAMCTRL_TEMP_SENSOR #define BF_DIGCTL_RAMCTRL_TEMP_SENSOR_V(e) BF_DIGCTL_RAMCTRL_TEMP_SENSOR(BV_DIGCTL_RAMCTRL_TEMP_SENSOR__##e) #define BFM_DIGCTL_RAMCTRL_TEMP_SENSOR_V(v) BM_DIGCTL_RAMCTRL_TEMP_SENSOR #define BP_DIGCTL_RAMCTRL_TEST_TEMP_COMP 16 #define BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP 0x70000 #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__LOW_TEMP 0x1 #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_A 0x2 #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_B 0x3 #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_C 0x4 #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_D 0x5 #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_E 0x6 #define BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__RANGE_F 0x7 #define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v) (((v) & 0x7) << 16) #define BFM_DIGCTL_RAMCTRL_TEST_TEMP_COMP(v) BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP #define BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(e) BF_DIGCTL_RAMCTRL_TEST_TEMP_COMP(BV_DIGCTL_RAMCTRL_TEST_TEMP_COMP__##e) #define BFM_DIGCTL_RAMCTRL_TEST_TEMP_COMP_V(v) BM_DIGCTL_RAMCTRL_TEST_TEMP_COMP #define BP_DIGCTL_RAMCTRL_SHIFT_COUNT 8 #define BM_DIGCTL_RAMCTRL_SHIFT_COUNT 0x7f00 #define BF_DIGCTL_RAMCTRL_SHIFT_COUNT(v) (((v) & 0x7f) << 8) #define BFM_DIGCTL_RAMCTRL_SHIFT_COUNT(v) BM_DIGCTL_RAMCTRL_SHIFT_COUNT #define BF_DIGCTL_RAMCTRL_SHIFT_COUNT_V(e) BF_DIGCTL_RAMCTRL_SHIFT_COUNT(BV_DIGCTL_RAMCTRL_SHIFT_COUNT__##e) #define BFM_DIGCTL_RAMCTRL_SHIFT_COUNT_V(v) BM_DIGCTL_RAMCTRL_SHIFT_COUNT #define BP_DIGCTL_RAMCTRL_FLIP_CLK 7 #define BM_DIGCTL_RAMCTRL_FLIP_CLK 0x80 #define BV_DIGCTL_RAMCTRL_FLIP_CLK__NORMAL 0x0 #define BV_DIGCTL_RAMCTRL_FLIP_CLK__INVERT 0x1 #define BF_DIGCTL_RAMCTRL_FLIP_CLK(v) (((v) & 0x1) << 7) #define BFM_DIGCTL_RAMCTRL_FLIP_CLK(v) BM_DIGCTL_RAMCTRL_FLIP_CLK #define BF_DIGCTL_RAMCTRL_FLIP_CLK_V(e) BF_DIGCTL_RAMCTRL_FLIP_CLK(BV_DIGCTL_RAMCTRL_FLIP_CLK__##e) #define BFM_DIGCTL_RAMCTRL_FLIP_CLK_V(v) BM_DIGCTL_RAMCTRL_FLIP_CLK #define BP_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 3 #define BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP 0x8 #define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__NORMAL 0x0 #define BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__OVER_RIDE 0x1 #define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v) (((v) & 0x1) << 3) #define BFM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(v) BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP #define BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(e) BF_DIGCTL_RAMCTRL_OVER_RIDE_TEMP(BV_DIGCTL_RAMCTRL_OVER_RIDE_TEMP__##e) #define BFM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP_V(v) BM_DIGCTL_RAMCTRL_OVER_RIDE_TEMP #define BP_DIGCTL_RAMCTRL_REF_CLK_GATE 2 #define BM_DIGCTL_RAMCTRL_REF_CLK_GATE 0x4 #define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__NORMAL 0x0 #define BV_DIGCTL_RAMCTRL_REF_CLK_GATE__OFF 0x1 #define BF_DIGCTL_RAMCTRL_REF_CLK_GATE(v) (((v) & 0x1) << 2) #define BFM_DIGCTL_RAMCTRL_REF_CLK_GATE(v) BM_DIGCTL_RAMCTRL_REF_CLK_GATE #define BF_DIGCTL_RAMCTRL_REF_CLK_GATE_V(e) BF_DIGCTL_RAMCTRL_REF_CLK_GATE(BV_DIGCTL_RAMCTRL_REF_CLK_GATE__##e) #define BFM_DIGCTL_RAMCTRL_REF_CLK_GATE_V(v) BM_DIGCTL_RAMCTRL_REF_CLK_GATE #define BP_DIGCTL_RAMCTRL_REPAIR_STATUS 1 #define BM_DIGCTL_RAMCTRL_REPAIR_STATUS 0x2 #define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__IDLE 0x0 #define BV_DIGCTL_RAMCTRL_REPAIR_STATUS__BUSY 0x1 #define BF_DIGCTL_RAMCTRL_REPAIR_STATUS(v) (((v) & 0x1) << 1) #define BFM_DIGCTL_RAMCTRL_REPAIR_STATUS(v) BM_DIGCTL_RAMCTRL_REPAIR_STATUS #define BF_DIGCTL_RAMCTRL_REPAIR_STATUS_V(e) BF_DIGCTL_RAMCTRL_REPAIR_STATUS(BV_DIGCTL_RAMCTRL_REPAIR_STATUS__##e) #define BFM_DIGCTL_RAMCTRL_REPAIR_STATUS_V(v) BM_DIGCTL_RAMCTRL_REPAIR_STATUS #define BP_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0 #define BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT 0x1 #define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__IDLE 0x0 #define BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__SEND 0x1 #define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v) (((v) & 0x1) << 0) #define BFM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(v) BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT #define BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(e) BF_DIGCTL_RAMCTRL_REPAIR_TRANSMIT(BV_DIGCTL_RAMCTRL_REPAIR_TRANSMIT__##e) #define BFM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT_V(v) BM_DIGCTL_RAMCTRL_REPAIR_TRANSMIT #define HW_DIGCTL_RAMREPAIR0 HW(DIGCTL_RAMREPAIR0) #define HWA_DIGCTL_RAMREPAIR0 (0x8001c000 + 0x40) #define HWT_DIGCTL_RAMREPAIR0 HWIO_32_RW #define HWN_DIGCTL_RAMREPAIR0 DIGCTL_RAMREPAIR0 #define HWI_DIGCTL_RAMREPAIR0 #define HW_DIGCTL_RAMREPAIR0_SET HW(DIGCTL_RAMREPAIR0_SET) #define HWA_DIGCTL_RAMREPAIR0_SET (HWA_DIGCTL_RAMREPAIR0 + 0x4) #define HWT_DIGCTL_RAMREPAIR0_SET HWIO_32_WO #define HWN_DIGCTL_RAMREPAIR0_SET DIGCTL_RAMREPAIR0 #define HWI_DIGCTL_RAMREPAIR0_SET #define HW_DIGCTL_RAMREPAIR0_CLR HW(DIGCTL_RAMREPAIR0_CLR) #define HWA_DIGCTL_RAMREPAIR0_CLR (HWA_DIGCTL_RAMREPAIR0 + 0x8) #define HWT_DIGCTL_RAMREPAIR0_CLR HWIO_32_WO #define HWN_DIGCTL_RAMREPAIR0_CLR DIGCTL_RAMREPAIR0 #define HWI_DIGCTL_RAMREPAIR0_CLR #define HW_DIGCTL_RAMREPAIR0_TOG HW(DIGCTL_RAMREPAIR0_TOG) #define HWA_DIGCTL_RAMREPAIR0_TOG (HWA_DIGCTL_RAMREPAIR0 + 0xc) #define HWT_DIGCTL_RAMREPAIR0_TOG HWIO_32_WO #define HWN_DIGCTL_RAMREPAIR0_TOG DIGCTL_RAMREPAIR0 #define HWI_DIGCTL_RAMREPAIR0_TOG #define BP_DIGCTL_RAMREPAIR0_EFUSE3 24 #define BM_DIGCTL_RAMREPAIR0_EFUSE3 0x7f000000 #define BF_DIGCTL_RAMREPAIR0_EFUSE3(v) (((v) & 0x7f) << 24) #define BFM_DIGCTL_RAMREPAIR0_EFUSE3(v) BM_DIGCTL_RAMREPAIR0_EFUSE3 #define BF_DIGCTL_RAMREPAIR0_EFUSE3_V(e) BF_DIGCTL_RAMREPAIR0_EFUSE3(BV_DIGCTL_RAMREPAIR0_EFUSE3__##e) #define BFM_DIGCTL_RAMREPAIR0_EFUSE3_V(v) BM_DIGCTL_RAMREPAIR0_EFUSE3 #define BP_DIGCTL_RAMREPAIR0_EFUSE2 16 #define BM_DIGCTL_RAMREPAIR0_EFUSE2 0x7f0000 #define BF_DIGCTL_RAMREPAIR0_EFUSE2(v) (((v) & 0x7f) << 16) #define BFM_DIGCTL_RAMREPAIR0_EFUSE2(v) BM_DIGCTL_RAMREPAIR0_EFUSE2 #define BF_DIGCTL_RAMREPAIR0_EFUSE2_V(e) BF_DIGCTL_RAMREPAIR0_EFUSE2(BV_DIGCTL_RAMREPAIR0_EFUSE2__##e) #define BFM_DIGCTL_RAMREPAIR0_EFUSE2_V(v) BM_DIGCTL_RAMREPAIR0_EFUSE2 #define BP_DIGCTL_RAMREPAIR0_EFUSE1 8 #define BM_DIGCTL_RAMREPAIR0_EFUSE1 0x7f00 #define BF_DIGCTL_RAMREPAIR0_EFUSE1(v) (((v) & 0x7f) << 8) #define BFM_DIGCTL_RAMREPAIR0_EFUSE1(v) BM_DIGCTL_RAMREPAIR0_EFUSE1 #define BF_DIGCTL_RAMREPAIR0_EFUSE1_V(e) BF_DIGCTL_RAMREPAIR0_EFUSE1(BV_DIGCTL_RAMREPAIR0_EFUSE1__##e) #define BFM_DIGCTL_RAMREPAIR0_EFUSE1_V(v) BM_DIGCTL_RAMREPAIR0_EFUSE1 #define BP_DIGCTL_RAMREPAIR0_EFUSE0 0 #define BM_DIGCTL_RAMREPAIR0_EFUSE0 0x7f #define BF_DIGCTL_RAMREPAIR0_EFUSE0(v) (((v) & 0x7f) << 0) #define BFM_DIGCTL_RAMREPAIR0_EFUSE0(v) BM_DIGCTL_RAMREPAIR0_EFUSE0 #define BF_DIGCTL_RAMREPAIR0_EFUSE0_V(e) BF_DIGCTL_RAMREPAIR0_EFUSE0(BV_DIGCTL_RAMREPAIR0_EFUSE0__##e) #define BFM_DIGCTL_RAMREPAIR0_EFUSE0_V(v) BM_DIGCTL_RAMREPAIR0_EFUSE0 #define HW_DIGCTL_RAMREPAIR1 HW(DIGCTL_RAMREPAIR1) #define HWA_DIGCTL_RAMREPAIR1 (0x8001c000 + 0x50) #define HWT_DIGCTL_RAMREPAIR1 HWIO_32_RW #define HWN_DIGCTL_RAMREPAIR1 DIGCTL_RAMREPAIR1 #define HWI_DIGCTL_RAMREPAIR1 #define HW_DIGCTL_RAMREPAIR1_SET HW(DIGCTL_RAMREPAIR1_SET) #define HWA_DIGCTL_RAMREPAIR1_SET (HWA_DIGCTL_RAMREPAIR1 + 0x4) #define HWT_DIGCTL_RAMREPAIR1_SET HWIO_32_WO #define HWN_DIGCTL_RAMREPAIR1_SET DIGCTL_RAMREPAIR1 #define HWI_DIGCTL_RAMREPAIR1_SET #define HW_DIGCTL_RAMREPAIR1_CLR HW(DIGCTL_RAMREPAIR1_CLR) #define HWA_DIGCTL_RAMREPAIR1_CLR (HWA_DIGCTL_RAMREPAIR1 + 0x8) #define HWT_DIGCTL_RAMREPAIR1_CLR HWIO_32_WO #define HWN_DIGCTL_RAMREPAIR1_CLR DIGCTL_RAMREPAIR1 #define HWI_DIGCTL_RAMREPAIR1_CLR #define HW_DIGCTL_RAMREPAIR1_TOG HW(DIGCTL_RAMREPAIR1_TOG) #define HWA_DIGCTL_RAMREPAIR1_TOG (HWA_DIGCTL_RAMREPAIR1 + 0xc) #define HWT_DIGCTL_RAMREPAIR1_TOG HWIO_32_WO #define HWN_DIGCTL_RAMREPAIR1_TOG DIGCTL_RAMREPAIR1 #define HWI_DIGCTL_RAMREPAIR1_TOG #define BP_DIGCTL_RAMREPAIR1_EFUSE3 24 #define BM_DIGCTL_RAMREPAIR1_EFUSE3 0x7f000000 #define BF_DIGCTL_RAMREPAIR1_EFUSE3(v) (((v) & 0x7f) << 24) #define BFM_DIGCTL_RAMREPAIR1_EFUSE3(v) BM_DIGCTL_RAMREPAIR1_EFUSE3 #define BF_DIGCTL_RAMREPAIR1_EFUSE3_V(e) BF_DIGCTL_RAMREPAIR1_EFUSE3(BV_DIGCTL_RAMREPAIR1_EFUSE3__##e) #define BFM_DIGCTL_RAMREPAIR1_EFUSE3_V(v) BM_DIGCTL_RAMREPAIR1_EFUSE3 #define BP_DIGCTL_RAMREPAIR1_EFUSE2 16 #define BM_DIGCTL_RAMREPAIR1_EFUSE2 0x7f0000 #define BF_DIGCTL_RAMREPAIR1_EFUSE2(v) (((v) & 0x7f) << 16) #define BFM_DIGCTL_RAMREPAIR1_EFUSE2(v) BM_DIGCTL_RAMREPAIR1_EFUSE2 #define BF_DIGCTL_RAMREPAIR1_EFUSE2_V(e) BF_DIGCTL_RAMREPAIR1_EFUSE2(BV_DIGCTL_RAMREPAIR1_EFUSE2__##e) #define BFM_DIGCTL_RAMREPAIR1_EFUSE2_V(v) BM_DIGCTL_RAMREPAIR1_EFUSE2 #define BP_DIGCTL_RAMREPAIR1_EFUSE1 8 #define BM_DIGCTL_RAMREPAIR1_EFUSE1 0x7f00 #define BF_DIGCTL_RAMREPAIR1_EFUSE1(v) (((v) & 0x7f) << 8) #define BFM_DIGCTL_RAMREPAIR1_EFUSE1(v) BM_DIGCTL_RAMREPAIR1_EFUSE1 #define BF_DIGCTL_RAMREPAIR1_EFUSE1_V(e) BF_DIGCTL_RAMREPAIR1_EFUSE1(BV_DIGCTL_RAMREPAIR1_EFUSE1__##e) #define BFM_DIGCTL_RAMREPAIR1_EFUSE1_V(v) BM_DIGCTL_RAMREPAIR1_EFUSE1 #define BP_DIGCTL_RAMREPAIR1_EFUSE0 0 #define BM_DIGCTL_RAMREPAIR1_EFUSE0 0x7f #define BF_DIGCTL_RAMREPAIR1_EFUSE0(v) (((v) & 0x7f) << 0) #define BFM_DIGCTL_RAMREPAIR1_EFUSE0(v) BM_DIGCTL_RAMREPAIR1_EFUSE0 #define BF_DIGCTL_RAMREPAIR1_EFUSE0_V(e) BF_DIGCTL_RAMREPAIR1_EFUSE0(BV_DIGCTL_RAMREPAIR1_EFUSE0__##e) #define BFM_DIGCTL_RAMREPAIR1_EFUSE0_V(v) BM_DIGCTL_RAMREPAIR1_EFUSE0 #define HW_DIGCTL_WRITEONCE HW(DIGCTL_WRITEONCE) #define HWA_DIGCTL_WRITEONCE (0x8001c000 + 0x60) #define HWT_DIGCTL_WRITEONCE HWIO_32_RW #define HWN_DIGCTL_WRITEONCE DIGCTL_WRITEONCE #define HWI_DIGCTL_WRITEONCE #define BP_DIGCTL_WRITEONCE_BITS 0 #define BM_DIGCTL_WRITEONCE_BITS 0xffffffff #define BF_DIGCTL_WRITEONCE_BITS(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_WRITEONCE_BITS(v) BM_DIGCTL_WRITEONCE_BITS #define BF_DIGCTL_WRITEONCE_BITS_V(e) BF_DIGCTL_WRITEONCE_BITS(BV_DIGCTL_WRITEONCE_BITS__##e) #define BFM_DIGCTL_WRITEONCE_BITS_V(v) BM_DIGCTL_WRITEONCE_BITS #define HW_DIGCTL_AHBCYCLES HW(DIGCTL_AHBCYCLES) #define HWA_DIGCTL_AHBCYCLES (0x8001c000 + 0x70) #define HWT_DIGCTL_AHBCYCLES HWIO_32_RW #define HWN_DIGCTL_AHBCYCLES DIGCTL_AHBCYCLES #define HWI_DIGCTL_AHBCYCLES #define BP_DIGCTL_AHBCYCLES_COUNT 0 #define BM_DIGCTL_AHBCYCLES_COUNT 0xffffffff #define BF_DIGCTL_AHBCYCLES_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_AHBCYCLES_COUNT(v) BM_DIGCTL_AHBCYCLES_COUNT #define BF_DIGCTL_AHBCYCLES_COUNT_V(e) BF_DIGCTL_AHBCYCLES_COUNT(BV_DIGCTL_AHBCYCLES_COUNT__##e) #define BFM_DIGCTL_AHBCYCLES_COUNT_V(v) BM_DIGCTL_AHBCYCLES_COUNT #define HW_DIGCTL_AHBSTALLED HW(DIGCTL_AHBSTALLED) #define HWA_DIGCTL_AHBSTALLED (0x8001c000 + 0x80) #define HWT_DIGCTL_AHBSTALLED HWIO_32_RW #define HWN_DIGCTL_AHBSTALLED DIGCTL_AHBSTALLED #define HWI_DIGCTL_AHBSTALLED #define BP_DIGCTL_AHBSTALLED_COUNT 0 #define BM_DIGCTL_AHBSTALLED_COUNT 0xffffffff #define BF_DIGCTL_AHBSTALLED_COUNT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_AHBSTALLED_COUNT(v) BM_DIGCTL_AHBSTALLED_COUNT #define BF_DIGCTL_AHBSTALLED_COUNT_V(e) BF_DIGCTL_AHBSTALLED_COUNT(BV_DIGCTL_AHBSTALLED_COUNT__##e) #define BFM_DIGCTL_AHBSTALLED_COUNT_V(v) BM_DIGCTL_AHBSTALLED_COUNT #define HW_DIGCTL_ENTROPY HW(DIGCTL_ENTROPY) #define HWA_DIGCTL_ENTROPY (0x8001c000 + 0x90) #define HWT_DIGCTL_ENTROPY HWIO_32_RW #define HWN_DIGCTL_ENTROPY DIGCTL_ENTROPY #define HWI_DIGCTL_ENTROPY #define BP_DIGCTL_ENTROPY_VALUE 0 #define BM_DIGCTL_ENTROPY_VALUE 0xffffffff #define BF_DIGCTL_ENTROPY_VALUE(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_ENTROPY_VALUE(v) BM_DIGCTL_ENTROPY_VALUE #define BF_DIGCTL_ENTROPY_VALUE_V(e) BF_DIGCTL_ENTROPY_VALUE(BV_DIGCTL_ENTROPY_VALUE__##e) #define BFM_DIGCTL_ENTROPY_VALUE_V(v) BM_DIGCTL_ENTROPY_VALUE #define HW_DIGCTL_ROMSHIELD HW(DIGCTL_ROMSHIELD) #define HWA_DIGCTL_ROMSHIELD (0x8001c000 + 0xa0) #define HWT_DIGCTL_ROMSHIELD HWIO_32_RW #define HWN_DIGCTL_ROMSHIELD DIGCTL_ROMSHIELD #define HWI_DIGCTL_ROMSHIELD #define BP_DIGCTL_ROMSHIELD_WRITE_ONCE 0 #define BM_DIGCTL_ROMSHIELD_WRITE_ONCE 0x1 #define BF_DIGCTL_ROMSHIELD_WRITE_ONCE(v) (((v) & 0x1) << 0) #define BFM_DIGCTL_ROMSHIELD_WRITE_ONCE(v) BM_DIGCTL_ROMSHIELD_WRITE_ONCE #define BF_DIGCTL_ROMSHIELD_WRITE_ONCE_V(e) BF_DIGCTL_ROMSHIELD_WRITE_ONCE(BV_DIGCTL_ROMSHIELD_WRITE_ONCE__##e) #define BFM_DIGCTL_ROMSHIELD_WRITE_ONCE_V(v) BM_DIGCTL_ROMSHIELD_WRITE_ONCE #define HW_DIGCTL_MICROSECONDS HW(DIGCTL_MICROSECONDS) #define HWA_DIGCTL_MICROSECONDS (0x8001c000 + 0xb0) #define HWT_DIGCTL_MICROSECONDS HWIO_32_RW #define HWN_DIGCTL_MICROSECONDS DIGCTL_MICROSECONDS #define HWI_DIGCTL_MICROSECONDS #define HW_DIGCTL_MICROSECONDS_SET HW(DIGCTL_MICROSECONDS_SET) #define HWA_DIGCTL_MICROSECONDS_SET (HWA_DIGCTL_MICROSECONDS + 0x4) #define HWT_DIGCTL_MICROSECONDS_SET HWIO_32_WO #define HWN_DIGCTL_MICROSECONDS_SET DIGCTL_MICROSECONDS #define HWI_DIGCTL_MICROSECONDS_SET #define HW_DIGCTL_MICROSECONDS_CLR HW(DIGCTL_MICROSECONDS_CLR) #define HWA_DIGCTL_MICROSECONDS_CLR (HWA_DIGCTL_MICROSECONDS + 0x8) #define HWT_DIGCTL_MICROSECONDS_CLR HWIO_32_WO #define HWN_DIGCTL_MICROSECONDS_CLR DIGCTL_MICROSECONDS #define HWI_DIGCTL_MICROSECONDS_CLR #define HW_DIGCTL_MICROSECONDS_TOG HW(DIGCTL_MICROSECONDS_TOG) #define HWA_DIGCTL_MICROSECONDS_TOG (HWA_DIGCTL_MICROSECONDS + 0xc) #define HWT_DIGCTL_MICROSECONDS_TOG HWIO_32_WO #define HWN_DIGCTL_MICROSECONDS_TOG DIGCTL_MICROSECONDS #define HWI_DIGCTL_MICROSECONDS_TOG #define BP_DIGCTL_MICROSECONDS_VALUE 0 #define BM_DIGCTL_MICROSECONDS_VALUE 0xffffffff #define BF_DIGCTL_MICROSECONDS_VALUE(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_MICROSECONDS_VALUE(v) BM_DIGCTL_MICROSECONDS_VALUE #define BF_DIGCTL_MICROSECONDS_VALUE_V(e) BF_DIGCTL_MICROSECONDS_VALUE(BV_DIGCTL_MICROSECONDS_VALUE__##e) #define BFM_DIGCTL_MICROSECONDS_VALUE_V(v) BM_DIGCTL_MICROSECONDS_VALUE #define HW_DIGCTL_DBGRD HW(DIGCTL_DBGRD) #define HWA_DIGCTL_DBGRD (0x8001c000 + 0xc0) #define HWT_DIGCTL_DBGRD HWIO_32_RW #define HWN_DIGCTL_DBGRD DIGCTL_DBGRD #define HWI_DIGCTL_DBGRD #define BP_DIGCTL_DBGRD_COMPLEMENT 0 #define BM_DIGCTL_DBGRD_COMPLEMENT 0xffffffff #define BF_DIGCTL_DBGRD_COMPLEMENT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_DBGRD_COMPLEMENT(v) BM_DIGCTL_DBGRD_COMPLEMENT #define BF_DIGCTL_DBGRD_COMPLEMENT_V(e) BF_DIGCTL_DBGRD_COMPLEMENT(BV_DIGCTL_DBGRD_COMPLEMENT__##e) #define BFM_DIGCTL_DBGRD_COMPLEMENT_V(v) BM_DIGCTL_DBGRD_COMPLEMENT #define HW_DIGCTL_DBG HW(DIGCTL_DBG) #define HWA_DIGCTL_DBG (0x8001c000 + 0xd0) #define HWT_DIGCTL_DBG HWIO_32_RW #define HWN_DIGCTL_DBG DIGCTL_DBG #define HWI_DIGCTL_DBG #define BP_DIGCTL_DBG_VALUE 0 #define BM_DIGCTL_DBG_VALUE 0xffffffff #define BF_DIGCTL_DBG_VALUE(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_DBG_VALUE(v) BM_DIGCTL_DBG_VALUE #define BF_DIGCTL_DBG_VALUE_V(e) BF_DIGCTL_DBG_VALUE(BV_DIGCTL_DBG_VALUE__##e) #define BFM_DIGCTL_DBG_VALUE_V(v) BM_DIGCTL_DBG_VALUE #define HW_DIGCTL_1TRAM_BIST_CSR HW(DIGCTL_1TRAM_BIST_CSR) #define HWA_DIGCTL_1TRAM_BIST_CSR (0x8001c000 + 0xe0) #define HWT_DIGCTL_1TRAM_BIST_CSR HWIO_32_RW #define HWN_DIGCTL_1TRAM_BIST_CSR DIGCTL_1TRAM_BIST_CSR #define HWI_DIGCTL_1TRAM_BIST_CSR #define HW_DIGCTL_1TRAM_BIST_CSR_SET HW(DIGCTL_1TRAM_BIST_CSR_SET) #define HWA_DIGCTL_1TRAM_BIST_CSR_SET (HWA_DIGCTL_1TRAM_BIST_CSR + 0x4) #define HWT_DIGCTL_1TRAM_BIST_CSR_SET HWIO_32_WO #define HWN_DIGCTL_1TRAM_BIST_CSR_SET DIGCTL_1TRAM_BIST_CSR #define HWI_DIGCTL_1TRAM_BIST_CSR_SET #define HW_DIGCTL_1TRAM_BIST_CSR_CLR HW(DIGCTL_1TRAM_BIST_CSR_CLR) #define HWA_DIGCTL_1TRAM_BIST_CSR_CLR (HWA_DIGCTL_1TRAM_BIST_CSR + 0x8) #define HWT_DIGCTL_1TRAM_BIST_CSR_CLR HWIO_32_WO #define HWN_DIGCTL_1TRAM_BIST_CSR_CLR DIGCTL_1TRAM_BIST_CSR #define HWI_DIGCTL_1TRAM_BIST_CSR_CLR #define HW_DIGCTL_1TRAM_BIST_CSR_TOG HW(DIGCTL_1TRAM_BIST_CSR_TOG) #define HWA_DIGCTL_1TRAM_BIST_CSR_TOG (HWA_DIGCTL_1TRAM_BIST_CSR + 0xc) #define HWT_DIGCTL_1TRAM_BIST_CSR_TOG HWIO_32_WO #define HWN_DIGCTL_1TRAM_BIST_CSR_TOG DIGCTL_1TRAM_BIST_CSR #define HWI_DIGCTL_1TRAM_BIST_CSR_TOG #define BP_DIGCTL_1TRAM_BIST_CSR_FAIL 3 #define BM_DIGCTL_1TRAM_BIST_CSR_FAIL 0x8 #define BF_DIGCTL_1TRAM_BIST_CSR_FAIL(v) (((v) & 0x1) << 3) #define BFM_DIGCTL_1TRAM_BIST_CSR_FAIL(v) BM_DIGCTL_1TRAM_BIST_CSR_FAIL #define BF_DIGCTL_1TRAM_BIST_CSR_FAIL_V(e) BF_DIGCTL_1TRAM_BIST_CSR_FAIL(BV_DIGCTL_1TRAM_BIST_CSR_FAIL__##e) #define BFM_DIGCTL_1TRAM_BIST_CSR_FAIL_V(v) BM_DIGCTL_1TRAM_BIST_CSR_FAIL #define BP_DIGCTL_1TRAM_BIST_CSR_PASS 2 #define BM_DIGCTL_1TRAM_BIST_CSR_PASS 0x4 #define BF_DIGCTL_1TRAM_BIST_CSR_PASS(v) (((v) & 0x1) << 2) #define BFM_DIGCTL_1TRAM_BIST_CSR_PASS(v) BM_DIGCTL_1TRAM_BIST_CSR_PASS #define BF_DIGCTL_1TRAM_BIST_CSR_PASS_V(e) BF_DIGCTL_1TRAM_BIST_CSR_PASS(BV_DIGCTL_1TRAM_BIST_CSR_PASS__##e) #define BFM_DIGCTL_1TRAM_BIST_CSR_PASS_V(v) BM_DIGCTL_1TRAM_BIST_CSR_PASS #define BP_DIGCTL_1TRAM_BIST_CSR_DONE 1 #define BM_DIGCTL_1TRAM_BIST_CSR_DONE 0x2 #define BF_DIGCTL_1TRAM_BIST_CSR_DONE(v) (((v) & 0x1) << 1) #define BFM_DIGCTL_1TRAM_BIST_CSR_DONE(v) BM_DIGCTL_1TRAM_BIST_CSR_DONE #define BF_DIGCTL_1TRAM_BIST_CSR_DONE_V(e) BF_DIGCTL_1TRAM_BIST_CSR_DONE(BV_DIGCTL_1TRAM_BIST_CSR_DONE__##e) #define BFM_DIGCTL_1TRAM_BIST_CSR_DONE_V(v) BM_DIGCTL_1TRAM_BIST_CSR_DONE #define BP_DIGCTL_1TRAM_BIST_CSR_START 0 #define BM_DIGCTL_1TRAM_BIST_CSR_START 0x1 #define BF_DIGCTL_1TRAM_BIST_CSR_START(v) (((v) & 0x1) << 0) #define BFM_DIGCTL_1TRAM_BIST_CSR_START(v) BM_DIGCTL_1TRAM_BIST_CSR_START #define BF_DIGCTL_1TRAM_BIST_CSR_START_V(e) BF_DIGCTL_1TRAM_BIST_CSR_START(BV_DIGCTL_1TRAM_BIST_CSR_START__##e) #define BFM_DIGCTL_1TRAM_BIST_CSR_START_V(v) BM_DIGCTL_1TRAM_BIST_CSR_START #define HW_DIGCTL_1TRAM_BIST_REPAIR0 HW(DIGCTL_1TRAM_BIST_REPAIR0) #define HWA_DIGCTL_1TRAM_BIST_REPAIR0 (0x8001c000 + 0xf0) #define HWT_DIGCTL_1TRAM_BIST_REPAIR0 HWIO_32_RW #define HWN_DIGCTL_1TRAM_BIST_REPAIR0 DIGCTL_1TRAM_BIST_REPAIR0 #define HWI_DIGCTL_1TRAM_BIST_REPAIR0 #define HW_DIGCTL_1TRAM_BIST_REPAIR1 HW(DIGCTL_1TRAM_BIST_REPAIR1) #define HWA_DIGCTL_1TRAM_BIST_REPAIR1 (0x8001c000 + 0x100) #define HWT_DIGCTL_1TRAM_BIST_REPAIR1 HWIO_32_RW #define HWN_DIGCTL_1TRAM_BIST_REPAIR1 DIGCTL_1TRAM_BIST_REPAIR1 #define HWI_DIGCTL_1TRAM_BIST_REPAIR1 #define HW_DIGCTL_1TRAM_STATUS0 HW(DIGCTL_1TRAM_STATUS0) #define HWA_DIGCTL_1TRAM_STATUS0 (0x8001c000 + 0x110) #define HWT_DIGCTL_1TRAM_STATUS0 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS0 DIGCTL_1TRAM_STATUS0 #define HWI_DIGCTL_1TRAM_STATUS0 #define BP_DIGCTL_1TRAM_STATUS0_FAILDATA00 0 #define BM_DIGCTL_1TRAM_STATUS0_FAILDATA00 0xffffffff #define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS0_FAILDATA00(v) BM_DIGCTL_1TRAM_STATUS0_FAILDATA00 #define BF_DIGCTL_1TRAM_STATUS0_FAILDATA00_V(e) BF_DIGCTL_1TRAM_STATUS0_FAILDATA00(BV_DIGCTL_1TRAM_STATUS0_FAILDATA00__##e) #define BFM_DIGCTL_1TRAM_STATUS0_FAILDATA00_V(v) BM_DIGCTL_1TRAM_STATUS0_FAILDATA00 #define HW_DIGCTL_1TRAM_STATUS1 HW(DIGCTL_1TRAM_STATUS1) #define HWA_DIGCTL_1TRAM_STATUS1 (0x8001c000 + 0x120) #define HWT_DIGCTL_1TRAM_STATUS1 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS1 DIGCTL_1TRAM_STATUS1 #define HWI_DIGCTL_1TRAM_STATUS1 #define BP_DIGCTL_1TRAM_STATUS1_FAILDATA01 0 #define BM_DIGCTL_1TRAM_STATUS1_FAILDATA01 0xffffffff #define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS1_FAILDATA01(v) BM_DIGCTL_1TRAM_STATUS1_FAILDATA01 #define BF_DIGCTL_1TRAM_STATUS1_FAILDATA01_V(e) BF_DIGCTL_1TRAM_STATUS1_FAILDATA01(BV_DIGCTL_1TRAM_STATUS1_FAILDATA01__##e) #define BFM_DIGCTL_1TRAM_STATUS1_FAILDATA01_V(v) BM_DIGCTL_1TRAM_STATUS1_FAILDATA01 #define HW_DIGCTL_1TRAM_STATUS2 HW(DIGCTL_1TRAM_STATUS2) #define HWA_DIGCTL_1TRAM_STATUS2 (0x8001c000 + 0x130) #define HWT_DIGCTL_1TRAM_STATUS2 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS2 DIGCTL_1TRAM_STATUS2 #define HWI_DIGCTL_1TRAM_STATUS2 #define BP_DIGCTL_1TRAM_STATUS2_FAILDATA10 0 #define BM_DIGCTL_1TRAM_STATUS2_FAILDATA10 0xffffffff #define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS2_FAILDATA10(v) BM_DIGCTL_1TRAM_STATUS2_FAILDATA10 #define BF_DIGCTL_1TRAM_STATUS2_FAILDATA10_V(e) BF_DIGCTL_1TRAM_STATUS2_FAILDATA10(BV_DIGCTL_1TRAM_STATUS2_FAILDATA10__##e) #define BFM_DIGCTL_1TRAM_STATUS2_FAILDATA10_V(v) BM_DIGCTL_1TRAM_STATUS2_FAILDATA10 #define HW_DIGCTL_1TRAM_STATUS3 HW(DIGCTL_1TRAM_STATUS3) #define HWA_DIGCTL_1TRAM_STATUS3 (0x8001c000 + 0x140) #define HWT_DIGCTL_1TRAM_STATUS3 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS3 DIGCTL_1TRAM_STATUS3 #define HWI_DIGCTL_1TRAM_STATUS3 #define BP_DIGCTL_1TRAM_STATUS3_FAILDATA11 0 #define BM_DIGCTL_1TRAM_STATUS3_FAILDATA11 0xffffffff #define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS3_FAILDATA11(v) BM_DIGCTL_1TRAM_STATUS3_FAILDATA11 #define BF_DIGCTL_1TRAM_STATUS3_FAILDATA11_V(e) BF_DIGCTL_1TRAM_STATUS3_FAILDATA11(BV_DIGCTL_1TRAM_STATUS3_FAILDATA11__##e) #define BFM_DIGCTL_1TRAM_STATUS3_FAILDATA11_V(v) BM_DIGCTL_1TRAM_STATUS3_FAILDATA11 #define HW_DIGCTL_1TRAM_STATUS4 HW(DIGCTL_1TRAM_STATUS4) #define HWA_DIGCTL_1TRAM_STATUS4 (0x8001c000 + 0x150) #define HWT_DIGCTL_1TRAM_STATUS4 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS4 DIGCTL_1TRAM_STATUS4 #define HWI_DIGCTL_1TRAM_STATUS4 #define BP_DIGCTL_1TRAM_STATUS4_FAILDATA20 0 #define BM_DIGCTL_1TRAM_STATUS4_FAILDATA20 0xffffffff #define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS4_FAILDATA20(v) BM_DIGCTL_1TRAM_STATUS4_FAILDATA20 #define BF_DIGCTL_1TRAM_STATUS4_FAILDATA20_V(e) BF_DIGCTL_1TRAM_STATUS4_FAILDATA20(BV_DIGCTL_1TRAM_STATUS4_FAILDATA20__##e) #define BFM_DIGCTL_1TRAM_STATUS4_FAILDATA20_V(v) BM_DIGCTL_1TRAM_STATUS4_FAILDATA20 #define HW_DIGCTL_1TRAM_STATUS5 HW(DIGCTL_1TRAM_STATUS5) #define HWA_DIGCTL_1TRAM_STATUS5 (0x8001c000 + 0x160) #define HWT_DIGCTL_1TRAM_STATUS5 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS5 DIGCTL_1TRAM_STATUS5 #define HWI_DIGCTL_1TRAM_STATUS5 #define BP_DIGCTL_1TRAM_STATUS5_FAILDATA21 0 #define BM_DIGCTL_1TRAM_STATUS5_FAILDATA21 0xffffffff #define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS5_FAILDATA21(v) BM_DIGCTL_1TRAM_STATUS5_FAILDATA21 #define BF_DIGCTL_1TRAM_STATUS5_FAILDATA21_V(e) BF_DIGCTL_1TRAM_STATUS5_FAILDATA21(BV_DIGCTL_1TRAM_STATUS5_FAILDATA21__##e) #define BFM_DIGCTL_1TRAM_STATUS5_FAILDATA21_V(v) BM_DIGCTL_1TRAM_STATUS5_FAILDATA21 #define HW_DIGCTL_1TRAM_STATUS6 HW(DIGCTL_1TRAM_STATUS6) #define HWA_DIGCTL_1TRAM_STATUS6 (0x8001c000 + 0x170) #define HWT_DIGCTL_1TRAM_STATUS6 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS6 DIGCTL_1TRAM_STATUS6 #define HWI_DIGCTL_1TRAM_STATUS6 #define BP_DIGCTL_1TRAM_STATUS6_FAILDATA30 0 #define BM_DIGCTL_1TRAM_STATUS6_FAILDATA30 0xffffffff #define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS6_FAILDATA30(v) BM_DIGCTL_1TRAM_STATUS6_FAILDATA30 #define BF_DIGCTL_1TRAM_STATUS6_FAILDATA30_V(e) BF_DIGCTL_1TRAM_STATUS6_FAILDATA30(BV_DIGCTL_1TRAM_STATUS6_FAILDATA30__##e) #define BFM_DIGCTL_1TRAM_STATUS6_FAILDATA30_V(v) BM_DIGCTL_1TRAM_STATUS6_FAILDATA30 #define HW_DIGCTL_1TRAM_STATUS7 HW(DIGCTL_1TRAM_STATUS7) #define HWA_DIGCTL_1TRAM_STATUS7 (0x8001c000 + 0x180) #define HWT_DIGCTL_1TRAM_STATUS7 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS7 DIGCTL_1TRAM_STATUS7 #define HWI_DIGCTL_1TRAM_STATUS7 #define BP_DIGCTL_1TRAM_STATUS7_FAILDATA31 0 #define BM_DIGCTL_1TRAM_STATUS7_FAILDATA31 0xffffffff #define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS7_FAILDATA31(v) BM_DIGCTL_1TRAM_STATUS7_FAILDATA31 #define BF_DIGCTL_1TRAM_STATUS7_FAILDATA31_V(e) BF_DIGCTL_1TRAM_STATUS7_FAILDATA31(BV_DIGCTL_1TRAM_STATUS7_FAILDATA31__##e) #define BFM_DIGCTL_1TRAM_STATUS7_FAILDATA31_V(v) BM_DIGCTL_1TRAM_STATUS7_FAILDATA31 #define HW_DIGCTL_1TRAM_STATUS8 HW(DIGCTL_1TRAM_STATUS8) #define HWA_DIGCTL_1TRAM_STATUS8 (0x8001c000 + 0x190) #define HWT_DIGCTL_1TRAM_STATUS8 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS8 DIGCTL_1TRAM_STATUS8 #define HWI_DIGCTL_1TRAM_STATUS8 #define BP_DIGCTL_1TRAM_STATUS8_FAILADDR01 16 #define BM_DIGCTL_1TRAM_STATUS8_FAILADDR01 0xffff0000 #define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(v) (((v) & 0xffff) << 16) #define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR01(v) BM_DIGCTL_1TRAM_STATUS8_FAILADDR01 #define BF_DIGCTL_1TRAM_STATUS8_FAILADDR01_V(e) BF_DIGCTL_1TRAM_STATUS8_FAILADDR01(BV_DIGCTL_1TRAM_STATUS8_FAILADDR01__##e) #define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR01_V(v) BM_DIGCTL_1TRAM_STATUS8_FAILADDR01 #define BP_DIGCTL_1TRAM_STATUS8_FAILADDR00 0 #define BM_DIGCTL_1TRAM_STATUS8_FAILADDR00 0xffff #define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(v) (((v) & 0xffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR00(v) BM_DIGCTL_1TRAM_STATUS8_FAILADDR00 #define BF_DIGCTL_1TRAM_STATUS8_FAILADDR00_V(e) BF_DIGCTL_1TRAM_STATUS8_FAILADDR00(BV_DIGCTL_1TRAM_STATUS8_FAILADDR00__##e) #define BFM_DIGCTL_1TRAM_STATUS8_FAILADDR00_V(v) BM_DIGCTL_1TRAM_STATUS8_FAILADDR00 #define HW_DIGCTL_1TRAM_STATUS9 HW(DIGCTL_1TRAM_STATUS9) #define HWA_DIGCTL_1TRAM_STATUS9 (0x8001c000 + 0x1a0) #define HWT_DIGCTL_1TRAM_STATUS9 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS9 DIGCTL_1TRAM_STATUS9 #define HWI_DIGCTL_1TRAM_STATUS9 #define BP_DIGCTL_1TRAM_STATUS9_FAILADDR11 16 #define BM_DIGCTL_1TRAM_STATUS9_FAILADDR11 0xffff0000 #define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(v) (((v) & 0xffff) << 16) #define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR11(v) BM_DIGCTL_1TRAM_STATUS9_FAILADDR11 #define BF_DIGCTL_1TRAM_STATUS9_FAILADDR11_V(e) BF_DIGCTL_1TRAM_STATUS9_FAILADDR11(BV_DIGCTL_1TRAM_STATUS9_FAILADDR11__##e) #define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR11_V(v) BM_DIGCTL_1TRAM_STATUS9_FAILADDR11 #define BP_DIGCTL_1TRAM_STATUS9_FAILADDR10 0 #define BM_DIGCTL_1TRAM_STATUS9_FAILADDR10 0xffff #define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(v) (((v) & 0xffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR10(v) BM_DIGCTL_1TRAM_STATUS9_FAILADDR10 #define BF_DIGCTL_1TRAM_STATUS9_FAILADDR10_V(e) BF_DIGCTL_1TRAM_STATUS9_FAILADDR10(BV_DIGCTL_1TRAM_STATUS9_FAILADDR10__##e) #define BFM_DIGCTL_1TRAM_STATUS9_FAILADDR10_V(v) BM_DIGCTL_1TRAM_STATUS9_FAILADDR10 #define HW_DIGCTL_1TRAM_STATUS10 HW(DIGCTL_1TRAM_STATUS10) #define HWA_DIGCTL_1TRAM_STATUS10 (0x8001c000 + 0x1b0) #define HWT_DIGCTL_1TRAM_STATUS10 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS10 DIGCTL_1TRAM_STATUS10 #define HWI_DIGCTL_1TRAM_STATUS10 #define BP_DIGCTL_1TRAM_STATUS10_FAILADDR21 16 #define BM_DIGCTL_1TRAM_STATUS10_FAILADDR21 0xffff0000 #define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(v) (((v) & 0xffff) << 16) #define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR21(v) BM_DIGCTL_1TRAM_STATUS10_FAILADDR21 #define BF_DIGCTL_1TRAM_STATUS10_FAILADDR21_V(e) BF_DIGCTL_1TRAM_STATUS10_FAILADDR21(BV_DIGCTL_1TRAM_STATUS10_FAILADDR21__##e) #define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR21_V(v) BM_DIGCTL_1TRAM_STATUS10_FAILADDR21 #define BP_DIGCTL_1TRAM_STATUS10_FAILADDR20 0 #define BM_DIGCTL_1TRAM_STATUS10_FAILADDR20 0xffff #define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(v) (((v) & 0xffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR20(v) BM_DIGCTL_1TRAM_STATUS10_FAILADDR20 #define BF_DIGCTL_1TRAM_STATUS10_FAILADDR20_V(e) BF_DIGCTL_1TRAM_STATUS10_FAILADDR20(BV_DIGCTL_1TRAM_STATUS10_FAILADDR20__##e) #define BFM_DIGCTL_1TRAM_STATUS10_FAILADDR20_V(v) BM_DIGCTL_1TRAM_STATUS10_FAILADDR20 #define HW_DIGCTL_1TRAM_STATUS11 HW(DIGCTL_1TRAM_STATUS11) #define HWA_DIGCTL_1TRAM_STATUS11 (0x8001c000 + 0x1c0) #define HWT_DIGCTL_1TRAM_STATUS11 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS11 DIGCTL_1TRAM_STATUS11 #define HWI_DIGCTL_1TRAM_STATUS11 #define BP_DIGCTL_1TRAM_STATUS11_FAILADDR31 16 #define BM_DIGCTL_1TRAM_STATUS11_FAILADDR31 0xffff0000 #define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(v) (((v) & 0xffff) << 16) #define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR31(v) BM_DIGCTL_1TRAM_STATUS11_FAILADDR31 #define BF_DIGCTL_1TRAM_STATUS11_FAILADDR31_V(e) BF_DIGCTL_1TRAM_STATUS11_FAILADDR31(BV_DIGCTL_1TRAM_STATUS11_FAILADDR31__##e) #define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR31_V(v) BM_DIGCTL_1TRAM_STATUS11_FAILADDR31 #define BP_DIGCTL_1TRAM_STATUS11_FAILADDR30 0 #define BM_DIGCTL_1TRAM_STATUS11_FAILADDR30 0xffff #define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(v) (((v) & 0xffff) << 0) #define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR30(v) BM_DIGCTL_1TRAM_STATUS11_FAILADDR30 #define BF_DIGCTL_1TRAM_STATUS11_FAILADDR30_V(e) BF_DIGCTL_1TRAM_STATUS11_FAILADDR30(BV_DIGCTL_1TRAM_STATUS11_FAILADDR30__##e) #define BFM_DIGCTL_1TRAM_STATUS11_FAILADDR30_V(v) BM_DIGCTL_1TRAM_STATUS11_FAILADDR30 #define HW_DIGCTL_1TRAM_STATUS12 HW(DIGCTL_1TRAM_STATUS12) #define HWA_DIGCTL_1TRAM_STATUS12 (0x8001c000 + 0x1d0) #define HWT_DIGCTL_1TRAM_STATUS12 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS12 DIGCTL_1TRAM_STATUS12 #define HWI_DIGCTL_1TRAM_STATUS12 #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE11 24 #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11 0x1f000000 #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v) (((v) & 0x1f) << 24) #define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE11(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11 #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11_V(e) BF_DIGCTL_1TRAM_STATUS12_FAILSTATE11(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE11__##e) #define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE11_V(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE11 #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE10 16 #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10 0x1f0000 #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v) (((v) & 0x1f) << 16) #define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE10(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10 #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10_V(e) BF_DIGCTL_1TRAM_STATUS12_FAILSTATE10(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE10__##e) #define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE10_V(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE10 #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE01 8 #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01 0x1f00 #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v) (((v) & 0x1f) << 8) #define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE01(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01 #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01_V(e) BF_DIGCTL_1TRAM_STATUS12_FAILSTATE01(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE01__##e) #define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE01_V(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE01 #define BP_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0 #define BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00 0x1f #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v) (((v) & 0x1f) << 0) #define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE00(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00 #define BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00_V(e) BF_DIGCTL_1TRAM_STATUS12_FAILSTATE00(BV_DIGCTL_1TRAM_STATUS12_FAILSTATE00__##e) #define BFM_DIGCTL_1TRAM_STATUS12_FAILSTATE00_V(v) BM_DIGCTL_1TRAM_STATUS12_FAILSTATE00 #define HW_DIGCTL_1TRAM_STATUS13 HW(DIGCTL_1TRAM_STATUS13) #define HWA_DIGCTL_1TRAM_STATUS13 (0x8001c000 + 0x1e0) #define HWT_DIGCTL_1TRAM_STATUS13 HWIO_32_RW #define HWN_DIGCTL_1TRAM_STATUS13 DIGCTL_1TRAM_STATUS13 #define HWI_DIGCTL_1TRAM_STATUS13 #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE31 24 #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31 0x1f000000 #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v) (((v) & 0x1f) << 24) #define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE31(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31 #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31_V(e) BF_DIGCTL_1TRAM_STATUS13_FAILSTATE31(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE31__##e) #define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE31_V(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE31 #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE30 16 #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30 0x1f0000 #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v) (((v) & 0x1f) << 16) #define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE30(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30 #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30_V(e) BF_DIGCTL_1TRAM_STATUS13_FAILSTATE30(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE30__##e) #define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE30_V(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE30 #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE21 8 #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21 0x1f00 #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v) (((v) & 0x1f) << 8) #define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE21(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21 #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21_V(e) BF_DIGCTL_1TRAM_STATUS13_FAILSTATE21(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE21__##e) #define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE21_V(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE21 #define BP_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0 #define BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20 0x1f #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v) (((v) & 0x1f) << 0) #define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE20(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20 #define BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20_V(e) BF_DIGCTL_1TRAM_STATUS13_FAILSTATE20(BV_DIGCTL_1TRAM_STATUS13_FAILSTATE20__##e) #define BFM_DIGCTL_1TRAM_STATUS13_FAILSTATE20_V(v) BM_DIGCTL_1TRAM_STATUS13_FAILSTATE20 #define HW_DIGCTL_SCRATCH0 HW(DIGCTL_SCRATCH0) #define HWA_DIGCTL_SCRATCH0 (0x8001c000 + 0x290) #define HWT_DIGCTL_SCRATCH0 HWIO_32_RW #define HWN_DIGCTL_SCRATCH0 DIGCTL_SCRATCH0 #define HWI_DIGCTL_SCRATCH0 #define BP_DIGCTL_SCRATCH0_PTR 0 #define BM_DIGCTL_SCRATCH0_PTR 0xffffffff #define BF_DIGCTL_SCRATCH0_PTR(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_SCRATCH0_PTR(v) BM_DIGCTL_SCRATCH0_PTR #define BF_DIGCTL_SCRATCH0_PTR_V(e) BF_DIGCTL_SCRATCH0_PTR(BV_DIGCTL_SCRATCH0_PTR__##e) #define BFM_DIGCTL_SCRATCH0_PTR_V(v) BM_DIGCTL_SCRATCH0_PTR #define HW_DIGCTL_SCRATCH1 HW(DIGCTL_SCRATCH1) #define HWA_DIGCTL_SCRATCH1 (0x8001c000 + 0x2a0) #define HWT_DIGCTL_SCRATCH1 HWIO_32_RW #define HWN_DIGCTL_SCRATCH1 DIGCTL_SCRATCH1 #define HWI_DIGCTL_SCRATCH1 #define BP_DIGCTL_SCRATCH1_PTR 0 #define BM_DIGCTL_SCRATCH1_PTR 0xffffffff #define BF_DIGCTL_SCRATCH1_PTR(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_SCRATCH1_PTR(v) BM_DIGCTL_SCRATCH1_PTR #define BF_DIGCTL_SCRATCH1_PTR_V(e) BF_DIGCTL_SCRATCH1_PTR(BV_DIGCTL_SCRATCH1_PTR__##e) #define BFM_DIGCTL_SCRATCH1_PTR_V(v) BM_DIGCTL_SCRATCH1_PTR #define HW_DIGCTL_ARMCACHE HW(DIGCTL_ARMCACHE) #define HWA_DIGCTL_ARMCACHE (0x8001c000 + 0x2b0) #define HWT_DIGCTL_ARMCACHE HWIO_32_RW #define HWN_DIGCTL_ARMCACHE DIGCTL_ARMCACHE #define HWI_DIGCTL_ARMCACHE #define BP_DIGCTL_ARMCACHE_CACHE_SS 8 #define BM_DIGCTL_ARMCACHE_CACHE_SS 0x300 #define BF_DIGCTL_ARMCACHE_CACHE_SS(v) (((v) & 0x3) << 8) #define BFM_DIGCTL_ARMCACHE_CACHE_SS(v) BM_DIGCTL_ARMCACHE_CACHE_SS #define BF_DIGCTL_ARMCACHE_CACHE_SS_V(e) BF_DIGCTL_ARMCACHE_CACHE_SS(BV_DIGCTL_ARMCACHE_CACHE_SS__##e) #define BFM_DIGCTL_ARMCACHE_CACHE_SS_V(v) BM_DIGCTL_ARMCACHE_CACHE_SS #define BP_DIGCTL_ARMCACHE_DTAG_SS 4 #define BM_DIGCTL_ARMCACHE_DTAG_SS 0x30 #define BF_DIGCTL_ARMCACHE_DTAG_SS(v) (((v) & 0x3) << 4) #define BFM_DIGCTL_ARMCACHE_DTAG_SS(v) BM_DIGCTL_ARMCACHE_DTAG_SS #define BF_DIGCTL_ARMCACHE_DTAG_SS_V(e) BF_DIGCTL_ARMCACHE_DTAG_SS(BV_DIGCTL_ARMCACHE_DTAG_SS__##e) #define BFM_DIGCTL_ARMCACHE_DTAG_SS_V(v) BM_DIGCTL_ARMCACHE_DTAG_SS #define BP_DIGCTL_ARMCACHE_ITAG_SS 0 #define BM_DIGCTL_ARMCACHE_ITAG_SS 0x3 #define BF_DIGCTL_ARMCACHE_ITAG_SS(v) (((v) & 0x3) << 0) #define BFM_DIGCTL_ARMCACHE_ITAG_SS(v) BM_DIGCTL_ARMCACHE_ITAG_SS #define BF_DIGCTL_ARMCACHE_ITAG_SS_V(e) BF_DIGCTL_ARMCACHE_ITAG_SS(BV_DIGCTL_ARMCACHE_ITAG_SS__##e) #define BFM_DIGCTL_ARMCACHE_ITAG_SS_V(v) BM_DIGCTL_ARMCACHE_ITAG_SS #define HW_DIGCTL_SGTL HW(DIGCTL_SGTL) #define HWA_DIGCTL_SGTL (0x8001c000 + 0x300) #define HWT_DIGCTL_SGTL HWIO_32_RW #define HWN_DIGCTL_SGTL DIGCTL_SGTL #define HWI_DIGCTL_SGTL #define BP_DIGCTL_SGTL_COPYRIGHT 0 #define BM_DIGCTL_SGTL_COPYRIGHT 0xffffffff #define BF_DIGCTL_SGTL_COPYRIGHT(v) (((v) & 0xffffffff) << 0) #define BFM_DIGCTL_SGTL_COPYRIGHT(v) BM_DIGCTL_SGTL_COPYRIGHT #define BF_DIGCTL_SGTL_COPYRIGHT_V(e) BF_DIGCTL_SGTL_COPYRIGHT(BV_DIGCTL_SGTL_COPYRIGHT__##e) #define BFM_DIGCTL_SGTL_COPYRIGHT_V(v) BM_DIGCTL_SGTL_COPYRIGHT #define HW_DIGCTL_CHIPID HW(DIGCTL_CHIPID) #define HWA_DIGCTL_CHIPID (0x8001c000 + 0x310) #define HWT_DIGCTL_CHIPID HWIO_32_RW #define HWN_DIGCTL_CHIPID DIGCTL_CHIPID #define HWI_DIGCTL_CHIPID #define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 #define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xffff0000 #define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) (((v) & 0xffff) << 16) #define BFM_DIGCTL_CHIPID_PRODUCT_CODE(v) BM_DIGCTL_CHIPID_PRODUCT_CODE #define BF_DIGCTL_CHIPID_PRODUCT_CODE_V(e) BF_DIGCTL_CHIPID_PRODUCT_CODE(BV_DIGCTL_CHIPID_PRODUCT_CODE__##e) #define BFM_DIGCTL_CHIPID_PRODUCT_CODE_V(v) BM_DIGCTL_CHIPID_PRODUCT_CODE #define BP_DIGCTL_CHIPID_REVISION 0 #define BM_DIGCTL_CHIPID_REVISION 0xff #define BF_DIGCTL_CHIPID_REVISION(v) (((v) & 0xff) << 0) #define BFM_DIGCTL_CHIPID_REVISION(v) BM_DIGCTL_CHIPID_REVISION #define BF_DIGCTL_CHIPID_REVISION_V(e) BF_DIGCTL_CHIPID_REVISION(BV_DIGCTL_CHIPID_REVISION__##e) #define BFM_DIGCTL_CHIPID_REVISION_V(v) BM_DIGCTL_CHIPID_REVISION #endif /* __HEADERGEN_STMP3600_DIGCTL_H__*/