/*************************************************************************** * __________ __ ___. * Open \______ \ ____ ____ | | _\_ |__ _______ ___ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. * headergen version: 3.0.0 * stmp3700 version: 2.4.0 * stmp3700 authors: Amaury Pouly * * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * ****************************************************************************/ #ifndef __HEADERGEN_STMP3700_GPIOMON_H__ #define __HEADERGEN_STMP3700_GPIOMON_H__ #define HW_GPIOMON_BANK0_DATAIN HW(GPIOMON_BANK0_DATAIN) #define HWA_GPIOMON_BANK0_DATAIN (0x8003c300 + 0x0) #define HWT_GPIOMON_BANK0_DATAIN HWIO_32_RW #define HWN_GPIOMON_BANK0_DATAIN GPIOMON_BANK0_DATAIN #define HWI_GPIOMON_BANK0_DATAIN #define BP_GPIOMON_BANK0_DATAIN_DATA 0 #define BM_GPIOMON_BANK0_DATAIN_DATA 0xffffffff #define BF_GPIOMON_BANK0_DATAIN_DATA(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK0_DATAIN_DATA(v) BM_GPIOMON_BANK0_DATAIN_DATA #define BF_GPIOMON_BANK0_DATAIN_DATA_V(e) BF_GPIOMON_BANK0_DATAIN_DATA(BV_GPIOMON_BANK0_DATAIN_DATA__##e) #define BFM_GPIOMON_BANK0_DATAIN_DATA_V(v) BM_GPIOMON_BANK0_DATAIN_DATA #define HW_GPIOMON_BANK1_DATAIN HW(GPIOMON_BANK1_DATAIN) #define HWA_GPIOMON_BANK1_DATAIN (0x8003c300 + 0x10) #define HWT_GPIOMON_BANK1_DATAIN HWIO_32_RW #define HWN_GPIOMON_BANK1_DATAIN GPIOMON_BANK1_DATAIN #define HWI_GPIOMON_BANK1_DATAIN #define BP_GPIOMON_BANK1_DATAIN_DATA 0 #define BM_GPIOMON_BANK1_DATAIN_DATA 0xffffffff #define BF_GPIOMON_BANK1_DATAIN_DATA(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK1_DATAIN_DATA(v) BM_GPIOMON_BANK1_DATAIN_DATA #define BF_GPIOMON_BANK1_DATAIN_DATA_V(e) BF_GPIOMON_BANK1_DATAIN_DATA(BV_GPIOMON_BANK1_DATAIN_DATA__##e) #define BFM_GPIOMON_BANK1_DATAIN_DATA_V(v) BM_GPIOMON_BANK1_DATAIN_DATA #define HW_GPIOMON_BANK2_DATAIN HW(GPIOMON_BANK2_DATAIN) #define HWA_GPIOMON_BANK2_DATAIN (0x8003c300 + 0x20) #define HWT_GPIOMON_BANK2_DATAIN HWIO_32_RW #define HWN_GPIOMON_BANK2_DATAIN GPIOMON_BANK2_DATAIN #define HWI_GPIOMON_BANK2_DATAIN #define BP_GPIOMON_BANK2_DATAIN_DATA 0 #define BM_GPIOMON_BANK2_DATAIN_DATA 0xffffffff #define BF_GPIOMON_BANK2_DATAIN_DATA(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK2_DATAIN_DATA(v) BM_GPIOMON_BANK2_DATAIN_DATA #define BF_GPIOMON_BANK2_DATAIN_DATA_V(e) BF_GPIOMON_BANK2_DATAIN_DATA(BV_GPIOMON_BANK2_DATAIN_DATA__##e) #define BFM_GPIOMON_BANK2_DATAIN_DATA_V(v) BM_GPIOMON_BANK2_DATAIN_DATA #define HW_GPIOMON_BANK3_DATAIN HW(GPIOMON_BANK3_DATAIN) #define HWA_GPIOMON_BANK3_DATAIN (0x8003c300 + 0x30) #define HWT_GPIOMON_BANK3_DATAIN HWIO_32_RW #define HWN_GPIOMON_BANK3_DATAIN GPIOMON_BANK3_DATAIN #define HWI_GPIOMON_BANK3_DATAIN #define BP_GPIOMON_BANK3_DATAIN_DATA 0 #define BM_GPIOMON_BANK3_DATAIN_DATA 0xffffffff #define BF_GPIOMON_BANK3_DATAIN_DATA(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK3_DATAIN_DATA(v) BM_GPIOMON_BANK3_DATAIN_DATA #define BF_GPIOMON_BANK3_DATAIN_DATA_V(e) BF_GPIOMON_BANK3_DATAIN_DATA(BV_GPIOMON_BANK3_DATAIN_DATA__##e) #define BFM_GPIOMON_BANK3_DATAIN_DATA_V(v) BM_GPIOMON_BANK3_DATAIN_DATA #define HW_GPIOMON_BANK0_DATAOUT HW(GPIOMON_BANK0_DATAOUT) #define HWA_GPIOMON_BANK0_DATAOUT (0x8003c300 + 0x40) #define HWT_GPIOMON_BANK0_DATAOUT HWIO_32_RW #define HWN_GPIOMON_BANK0_DATAOUT GPIOMON_BANK0_DATAOUT #define HWI_GPIOMON_BANK0_DATAOUT #define HW_GPIOMON_BANK0_DATAOUT_SET HW(GPIOMON_BANK0_DATAOUT_SET) #define HWA_GPIOMON_BANK0_DATAOUT_SET (HWA_GPIOMON_BANK0_DATAOUT + 0x4) #define HWT_GPIOMON_BANK0_DATAOUT_SET HWIO_32_WO #define HWN_GPIOMON_BANK0_DATAOUT_SET GPIOMON_BANK0_DATAOUT #define HWI_GPIOMON_BANK0_DATAOUT_SET #define HW_GPIOMON_BANK0_DATAOUT_CLR HW(GPIOMON_BANK0_DATAOUT_CLR) #define HWA_GPIOMON_BANK0_DATAOUT_CLR (HWA_GPIOMON_BANK0_DATAOUT + 0x8) #define HWT_GPIOMON_BANK0_DATAOUT_CLR HWIO_32_WO #define HWN_GPIOMON_BANK0_DATAOUT_CLR GPIOMON_BANK0_DATAOUT #define HWI_GPIOMON_BANK0_DATAOUT_CLR #define HW_GPIOMON_BANK0_DATAOUT_TOG HW(GPIOMON_BANK0_DATAOUT_TOG) #define HWA_GPIOMON_BANK0_DATAOUT_TOG (HWA_GPIOMON_BANK0_DATAOUT + 0xc) #define HWT_GPIOMON_BANK0_DATAOUT_TOG HWIO_32_WO #define HWN_GPIOMON_BANK0_DATAOUT_TOG GPIOMON_BANK0_DATAOUT #define HWI_GPIOMON_BANK0_DATAOUT_TOG #define BP_GPIOMON_BANK0_DATAOUT_DATA 0 #define BM_GPIOMON_BANK0_DATAOUT_DATA 0xffffffff #define BF_GPIOMON_BANK0_DATAOUT_DATA(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK0_DATAOUT_DATA(v) BM_GPIOMON_BANK0_DATAOUT_DATA #define BF_GPIOMON_BANK0_DATAOUT_DATA_V(e) BF_GPIOMON_BANK0_DATAOUT_DATA(BV_GPIOMON_BANK0_DATAOUT_DATA__##e) #define BFM_GPIOMON_BANK0_DATAOUT_DATA_V(v) BM_GPIOMON_BANK0_DATAOUT_DATA #define HW_GPIOMON_BANK1_DATAOUT HW(GPIOMON_BANK1_DATAOUT) #define HWA_GPIOMON_BANK1_DATAOUT (0x8003c300 + 0x50) #define HWT_GPIOMON_BANK1_DATAOUT HWIO_32_RW #define HWN_GPIOMON_BANK1_DATAOUT GPIOMON_BANK1_DATAOUT #define HWI_GPIOMON_BANK1_DATAOUT #define HW_GPIOMON_BANK1_DATAOUT_SET HW(GPIOMON_BANK1_DATAOUT_SET) #define HWA_GPIOMON_BANK1_DATAOUT_SET (HWA_GPIOMON_BANK1_DATAOUT + 0x4) #define HWT_GPIOMON_BANK1_DATAOUT_SET HWIO_32_WO #define HWN_GPIOMON_BANK1_DATAOUT_SET GPIOMON_BANK1_DATAOUT #define HWI_GPIOMON_BANK1_DATAOUT_SET #define HW_GPIOMON_BANK1_DATAOUT_CLR HW(GPIOMON_BANK1_DATAOUT_CLR) #define HWA_GPIOMON_BANK1_DATAOUT_CLR (HWA_GPIOMON_BANK1_DATAOUT + 0x8) #define HWT_GPIOMON_BANK1_DATAOUT_CLR HWIO_32_WO #define HWN_GPIOMON_BANK1_DATAOUT_CLR GPIOMON_BANK1_DATAOUT #define HWI_GPIOMON_BANK1_DATAOUT_CLR #define HW_GPIOMON_BANK1_DATAOUT_TOG HW(GPIOMON_BANK1_DATAOUT_TOG) #define HWA_GPIOMON_BANK1_DATAOUT_TOG (HWA_GPIOMON_BANK1_DATAOUT + 0xc) #define HWT_GPIOMON_BANK1_DATAOUT_TOG HWIO_32_WO #define HWN_GPIOMON_BANK1_DATAOUT_TOG GPIOMON_BANK1_DATAOUT #define HWI_GPIOMON_BANK1_DATAOUT_TOG #define BP_GPIOMON_BANK1_DATAOUT_DATA 0 #define BM_GPIOMON_BANK1_DATAOUT_DATA 0xffffffff #define BF_GPIOMON_BANK1_DATAOUT_DATA(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK1_DATAOUT_DATA(v) BM_GPIOMON_BANK1_DATAOUT_DATA #define BF_GPIOMON_BANK1_DATAOUT_DATA_V(e) BF_GPIOMON_BANK1_DATAOUT_DATA(BV_GPIOMON_BANK1_DATAOUT_DATA__##e) #define BFM_GPIOMON_BANK1_DATAOUT_DATA_V(v) BM_GPIOMON_BANK1_DATAOUT_DATA #define HW_GPIOMON_BANK2_DATAOUT HW(GPIOMON_BANK2_DATAOUT) #define HWA_GPIOMON_BANK2_DATAOUT (0x8003c300 + 0x60) #define HWT_GPIOMON_BANK2_DATAOUT HWIO_32_RW #define HWN_GPIOMON_BANK2_DATAOUT GPIOMON_BANK2_DATAOUT #define HWI_GPIOMON_BANK2_DATAOUT #define HW_GPIOMON_BANK2_DATAOUT_SET HW(GPIOMON_BANK2_DATAOUT_SET) #define HWA_GPIOMON_BANK2_DATAOUT_SET (HWA_GPIOMON_BANK2_DATAOUT + 0x4) #define HWT_GPIOMON_BANK2_DATAOUT_SET HWIO_32_WO #define HWN_GPIOMON_BANK2_DATAOUT_SET GPIOMON_BANK2_DATAOUT #define HWI_GPIOMON_BANK2_DATAOUT_SET #define HW_GPIOMON_BANK2_DATAOUT_CLR HW(GPIOMON_BANK2_DATAOUT_CLR) #define HWA_GPIOMON_BANK2_DATAOUT_CLR (HWA_GPIOMON_BANK2_DATAOUT + 0x8) #define HWT_GPIOMON_BANK2_DATAOUT_CLR HWIO_32_WO #define HWN_GPIOMON_BANK2_DATAOUT_CLR GPIOMON_BANK2_DATAOUT #define HWI_GPIOMON_BANK2_DATAOUT_CLR #define HW_GPIOMON_BANK2_DATAOUT_TOG HW(GPIOMON_BANK2_DATAOUT_TOG) #define HWA_GPIOMON_BANK2_DATAOUT_TOG (HWA_GPIOMON_BANK2_DATAOUT + 0xc) #define HWT_GPIOMON_BANK2_DATAOUT_TOG HWIO_32_WO #define HWN_GPIOMON_BANK2_DATAOUT_TOG GPIOMON_BANK2_DATAOUT #define HWI_GPIOMON_BANK2_DATAOUT_TOG #define BP_GPIOMON_BANK2_DATAOUT_DATA 0 #define BM_GPIOMON_BANK2_DATAOUT_DATA 0xffffffff #define BF_GPIOMON_BANK2_DATAOUT_DATA(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK2_DATAOUT_DATA(v) BM_GPIOMON_BANK2_DATAOUT_DATA #define BF_GPIOMON_BANK2_DATAOUT_DATA_V(e) BF_GPIOMON_BANK2_DATAOUT_DATA(BV_GPIOMON_BANK2_DATAOUT_DATA__##e) #define BFM_GPIOMON_BANK2_DATAOUT_DATA_V(v) BM_GPIOMON_BANK2_DATAOUT_DATA #define HW_GPIOMON_BANK3_DATAOUT HW(GPIOMON_BANK3_DATAOUT) #define HWA_GPIOMON_BANK3_DATAOUT (0x8003c300 + 0x70) #define HWT_GPIOMON_BANK3_DATAOUT HWIO_32_RW #define HWN_GPIOMON_BANK3_DATAOUT GPIOMON_BANK3_DATAOUT #define HWI_GPIOMON_BANK3_DATAOUT #define HW_GPIOMON_BANK3_DATAOUT_SET HW(GPIOMON_BANK3_DATAOUT_SET) #define HWA_GPIOMON_BANK3_DATAOUT_SET (HWA_GPIOMON_BANK3_DATAOUT + 0x4) #define HWT_GPIOMON_BANK3_DATAOUT_SET HWIO_32_WO #define HWN_GPIOMON_BANK3_DATAOUT_SET GPIOMON_BANK3_DATAOUT #define HWI_GPIOMON_BANK3_DATAOUT_SET #define HW_GPIOMON_BANK3_DATAOUT_CLR HW(GPIOMON_BANK3_DATAOUT_CLR) #define HWA_GPIOMON_BANK3_DATAOUT_CLR (HWA_GPIOMON_BANK3_DATAOUT + 0x8) #define HWT_GPIOMON_BANK3_DATAOUT_CLR HWIO_32_WO #define HWN_GPIOMON_BANK3_DATAOUT_CLR GPIOMON_BANK3_DATAOUT #define HWI_GPIOMON_BANK3_DATAOUT_CLR #define HW_GPIOMON_BANK3_DATAOUT_TOG HW(GPIOMON_BANK3_DATAOUT_TOG) #define HWA_GPIOMON_BANK3_DATAOUT_TOG (HWA_GPIOMON_BANK3_DATAOUT + 0xc) #define HWT_GPIOMON_BANK3_DATAOUT_TOG HWIO_32_WO #define HWN_GPIOMON_BANK3_DATAOUT_TOG GPIOMON_BANK3_DATAOUT #define HWI_GPIOMON_BANK3_DATAOUT_TOG #define BP_GPIOMON_BANK3_DATAOUT_DATA 0 #define BM_GPIOMON_BANK3_DATAOUT_DATA 0xffffffff #define BF_GPIOMON_BANK3_DATAOUT_DATA(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK3_DATAOUT_DATA(v) BM_GPIOMON_BANK3_DATAOUT_DATA #define BF_GPIOMON_BANK3_DATAOUT_DATA_V(e) BF_GPIOMON_BANK3_DATAOUT_DATA(BV_GPIOMON_BANK3_DATAOUT_DATA__##e) #define BFM_GPIOMON_BANK3_DATAOUT_DATA_V(v) BM_GPIOMON_BANK3_DATAOUT_DATA #define HW_GPIOMON_BANK0_DATAOEN HW(GPIOMON_BANK0_DATAOEN) #define HWA_GPIOMON_BANK0_DATAOEN (0x8003c300 + 0x80) #define HWT_GPIOMON_BANK0_DATAOEN HWIO_32_RW #define HWN_GPIOMON_BANK0_DATAOEN GPIOMON_BANK0_DATAOEN #define HWI_GPIOMON_BANK0_DATAOEN #define HW_GPIOMON_BANK0_DATAOEN_SET HW(GPIOMON_BANK0_DATAOEN_SET) #define HWA_GPIOMON_BANK0_DATAOEN_SET (HWA_GPIOMON_BANK0_DATAOEN + 0x4) #define HWT_GPIOMON_BANK0_DATAOEN_SET HWIO_32_WO #define HWN_GPIOMON_BANK0_DATAOEN_SET GPIOMON_BANK0_DATAOEN #define HWI_GPIOMON_BANK0_DATAOEN_SET #define HW_GPIOMON_BANK0_DATAOEN_CLR HW(GPIOMON_BANK0_DATAOEN_CLR) #define HWA_GPIOMON_BANK0_DATAOEN_CLR (HWA_GPIOMON_BANK0_DATAOEN + 0x8) #define HWT_GPIOMON_BANK0_DATAOEN_CLR HWIO_32_WO #define HWN_GPIOMON_BANK0_DATAOEN_CLR GPIOMON_BANK0_DATAOEN #define HWI_GPIOMON_BANK0_DATAOEN_CLR #define HW_GPIOMON_BANK0_DATAOEN_TOG HW(GPIOMON_BANK0_DATAOEN_TOG) #define HWA_GPIOMON_BANK0_DATAOEN_TOG (HWA_GPIOMON_BANK0_DATAOEN + 0xc) #define HWT_GPIOMON_BANK0_DATAOEN_TOG HWIO_32_WO #define HWN_GPIOMON_BANK0_DATAOEN_TOG GPIOMON_BANK0_DATAOEN #define HWI_GPIOMON_BANK0_DATAOEN_TOG #define BP_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES 0 #define BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES 0xffffffff #define BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(v) BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES #define BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES_V(e) BF_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES(BV_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES__##e) #define BFM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES_V(v) BM_GPIOMON_BANK0_DATAOEN_OUTPUT_ENABLES #define HW_GPIOMON_BANK1_DATAOEN HW(GPIOMON_BANK1_DATAOEN) #define HWA_GPIOMON_BANK1_DATAOEN (0x8003c300 + 0x90) #define HWT_GPIOMON_BANK1_DATAOEN HWIO_32_RW #define HWN_GPIOMON_BANK1_DATAOEN GPIOMON_BANK1_DATAOEN #define HWI_GPIOMON_BANK1_DATAOEN #define HW_GPIOMON_BANK1_DATAOEN_SET HW(GPIOMON_BANK1_DATAOEN_SET) #define HWA_GPIOMON_BANK1_DATAOEN_SET (HWA_GPIOMON_BANK1_DATAOEN + 0x4) #define HWT_GPIOMON_BANK1_DATAOEN_SET HWIO_32_WO #define HWN_GPIOMON_BANK1_DATAOEN_SET GPIOMON_BANK1_DATAOEN #define HWI_GPIOMON_BANK1_DATAOEN_SET #define HW_GPIOMON_BANK1_DATAOEN_CLR HW(GPIOMON_BANK1_DATAOEN_CLR) #define HWA_GPIOMON_BANK1_DATAOEN_CLR (HWA_GPIOMON_BANK1_DATAOEN + 0x8) #define HWT_GPIOMON_BANK1_DATAOEN_CLR HWIO_32_WO #define HWN_GPIOMON_BANK1_DATAOEN_CLR GPIOMON_BANK1_DATAOEN #define HWI_GPIOMON_BANK1_DATAOEN_CLR #define HW_GPIOMON_BANK1_DATAOEN_TOG HW(GPIOMON_BANK1_DATAOEN_TOG) #define HWA_GPIOMON_BANK1_DATAOEN_TOG (HWA_GPIOMON_BANK1_DATAOEN + 0xc) #define HWT_GPIOMON_BANK1_DATAOEN_TOG HWIO_32_WO #define HWN_GPIOMON_BANK1_DATAOEN_TOG GPIOMON_BANK1_DATAOEN #define HWI_GPIOMON_BANK1_DATAOEN_TOG #define BP_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES 0 #define BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES 0xffffffff #define BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(v) BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES #define BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES_V(e) BF_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES(BV_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES__##e) #define BFM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES_V(v) BM_GPIOMON_BANK1_DATAOEN_OUTPUT_ENABLES #define HW_GPIOMON_BANK2_DATAOEN HW(GPIOMON_BANK2_DATAOEN) #define HWA_GPIOMON_BANK2_DATAOEN (0x8003c300 + 0xa0) #define HWT_GPIOMON_BANK2_DATAOEN HWIO_32_RW #define HWN_GPIOMON_BANK2_DATAOEN GPIOMON_BANK2_DATAOEN #define HWI_GPIOMON_BANK2_DATAOEN #define HW_GPIOMON_BANK2_DATAOEN_SET HW(GPIOMON_BANK2_DATAOEN_SET) #define HWA_GPIOMON_BANK2_DATAOEN_SET (HWA_GPIOMON_BANK2_DATAOEN + 0x4) #define HWT_GPIOMON_BANK2_DATAOEN_SET HWIO_32_WO #define HWN_GPIOMON_BANK2_DATAOEN_SET GPIOMON_BANK2_DATAOEN #define HWI_GPIOMON_BANK2_DATAOEN_SET #define HW_GPIOMON_BANK2_DATAOEN_CLR HW(GPIOMON_BANK2_DATAOEN_CLR) #define HWA_GPIOMON_BANK2_DATAOEN_CLR (HWA_GPIOMON_BANK2_DATAOEN + 0x8) #define HWT_GPIOMON_BANK2_DATAOEN_CLR HWIO_32_WO #define HWN_GPIOMON_BANK2_DATAOEN_CLR GPIOMON_BANK2_DATAOEN #define HWI_GPIOMON_BANK2_DATAOEN_CLR #define HW_GPIOMON_BANK2_DATAOEN_TOG HW(GPIOMON_BANK2_DATAOEN_TOG) #define HWA_GPIOMON_BANK2_DATAOEN_TOG (HWA_GPIOMON_BANK2_DATAOEN + 0xc) #define HWT_GPIOMON_BANK2_DATAOEN_TOG HWIO_32_WO #define HWN_GPIOMON_BANK2_DATAOEN_TOG GPIOMON_BANK2_DATAOEN #define HWI_GPIOMON_BANK2_DATAOEN_TOG #define BP_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES 0 #define BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES 0xffffffff #define BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(v) BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES #define BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES_V(e) BF_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES(BV_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES__##e) #define BFM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES_V(v) BM_GPIOMON_BANK2_DATAOEN_OUTPUT_ENABLES #define HW_GPIOMON_BANK3_DATAOEN HW(GPIOMON_BANK3_DATAOEN) #define HWA_GPIOMON_BANK3_DATAOEN (0x8003c300 + 0xb0) #define HWT_GPIOMON_BANK3_DATAOEN HWIO_32_RW #define HWN_GPIOMON_BANK3_DATAOEN GPIOMON_BANK3_DATAOEN #define HWI_GPIOMON_BANK3_DATAOEN #define HW_GPIOMON_BANK3_DATAOEN_SET HW(GPIOMON_BANK3_DATAOEN_SET) #define HWA_GPIOMON_BANK3_DATAOEN_SET (HWA_GPIOMON_BANK3_DATAOEN + 0x4) #define HWT_GPIOMON_BANK3_DATAOEN_SET HWIO_32_WO #define HWN_GPIOMON_BANK3_DATAOEN_SET GPIOMON_BANK3_DATAOEN #define HWI_GPIOMON_BANK3_DATAOEN_SET #define HW_GPIOMON_BANK3_DATAOEN_CLR HW(GPIOMON_BANK3_DATAOEN_CLR) #define HWA_GPIOMON_BANK3_DATAOEN_CLR (HWA_GPIOMON_BANK3_DATAOEN + 0x8) #define HWT_GPIOMON_BANK3_DATAOEN_CLR HWIO_32_WO #define HWN_GPIOMON_BANK3_DATAOEN_CLR GPIOMON_BANK3_DATAOEN #define HWI_GPIOMON_BANK3_DATAOEN_CLR #define HW_GPIOMON_BANK3_DATAOEN_TOG HW(GPIOMON_BANK3_DATAOEN_TOG) #define HWA_GPIOMON_BANK3_DATAOEN_TOG (HWA_GPIOMON_BANK3_DATAOEN + 0xc) #define HWT_GPIOMON_BANK3_DATAOEN_TOG HWIO_32_WO #define HWN_GPIOMON_BANK3_DATAOEN_TOG GPIOMON_BANK3_DATAOEN #define HWI_GPIOMON_BANK3_DATAOEN_TOG #define BP_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES 0 #define BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES 0xffffffff #define BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(v) BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES #define BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES_V(e) BF_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES(BV_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES__##e) #define BFM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES_V(v) BM_GPIOMON_BANK3_DATAOEN_OUTPUT_ENABLES #define HW_GPIOMON_CTRL HW(GPIOMON_CTRL) #define HWA_GPIOMON_CTRL (0x8003c300 + 0xc0) #define HWT_GPIOMON_CTRL HWIO_32_RW #define HWN_GPIOMON_CTRL GPIOMON_CTRL #define HWI_GPIOMON_CTRL #define HW_GPIOMON_CTRL_SET HW(GPIOMON_CTRL_SET) #define HWA_GPIOMON_CTRL_SET (HWA_GPIOMON_CTRL + 0x4) #define HWT_GPIOMON_CTRL_SET HWIO_32_WO #define HWN_GPIOMON_CTRL_SET GPIOMON_CTRL #define HWI_GPIOMON_CTRL_SET #define HW_GPIOMON_CTRL_CLR HW(GPIOMON_CTRL_CLR) #define HWA_GPIOMON_CTRL_CLR (HWA_GPIOMON_CTRL + 0x8) #define HWT_GPIOMON_CTRL_CLR HWIO_32_WO #define HWN_GPIOMON_CTRL_CLR GPIOMON_CTRL #define HWI_GPIOMON_CTRL_CLR #define HW_GPIOMON_CTRL_TOG HW(GPIOMON_CTRL_TOG) #define HWA_GPIOMON_CTRL_TOG (HWA_GPIOMON_CTRL + 0xc) #define HWT_GPIOMON_CTRL_TOG HWIO_32_WO #define HWN_GPIOMON_CTRL_TOG GPIOMON_CTRL #define HWI_GPIOMON_CTRL_TOG #define BP_GPIOMON_CTRL_RSRVD 4 #define BM_GPIOMON_CTRL_RSRVD 0xfffffff0 #define BF_GPIOMON_CTRL_RSRVD(v) (((v) & 0xfffffff) << 4) #define BFM_GPIOMON_CTRL_RSRVD(v) BM_GPIOMON_CTRL_RSRVD #define BF_GPIOMON_CTRL_RSRVD_V(e) BF_GPIOMON_CTRL_RSRVD(BV_GPIOMON_CTRL_RSRVD__##e) #define BFM_GPIOMON_CTRL_RSRVD_V(v) BM_GPIOMON_CTRL_RSRVD #define BP_GPIOMON_CTRL_PINMUX_ALT_RESET 3 #define BM_GPIOMON_CTRL_PINMUX_ALT_RESET 0x8 #define BF_GPIOMON_CTRL_PINMUX_ALT_RESET(v) (((v) & 0x1) << 3) #define BFM_GPIOMON_CTRL_PINMUX_ALT_RESET(v) BM_GPIOMON_CTRL_PINMUX_ALT_RESET #define BF_GPIOMON_CTRL_PINMUX_ALT_RESET_V(e) BF_GPIOMON_CTRL_PINMUX_ALT_RESET(BV_GPIOMON_CTRL_PINMUX_ALT_RESET__##e) #define BFM_GPIOMON_CTRL_PINMUX_ALT_RESET_V(v) BM_GPIOMON_CTRL_PINMUX_ALT_RESET #define BP_GPIOMON_CTRL_OEN_8MA 2 #define BM_GPIOMON_CTRL_OEN_8MA 0x4 #define BF_GPIOMON_CTRL_OEN_8MA(v) (((v) & 0x1) << 2) #define BFM_GPIOMON_CTRL_OEN_8MA(v) BM_GPIOMON_CTRL_OEN_8MA #define BF_GPIOMON_CTRL_OEN_8MA_V(e) BF_GPIOMON_CTRL_OEN_8MA(BV_GPIOMON_CTRL_OEN_8MA__##e) #define BFM_GPIOMON_CTRL_OEN_8MA_V(v) BM_GPIOMON_CTRL_OEN_8MA #define BP_GPIOMON_CTRL_OEN_4MA 1 #define BM_GPIOMON_CTRL_OEN_4MA 0x2 #define BF_GPIOMON_CTRL_OEN_4MA(v) (((v) & 0x1) << 1) #define BFM_GPIOMON_CTRL_OEN_4MA(v) BM_GPIOMON_CTRL_OEN_4MA #define BF_GPIOMON_CTRL_OEN_4MA_V(e) BF_GPIOMON_CTRL_OEN_4MA(BV_GPIOMON_CTRL_OEN_4MA__##e) #define BFM_GPIOMON_CTRL_OEN_4MA_V(v) BM_GPIOMON_CTRL_OEN_4MA #define BP_GPIOMON_CTRL_OEN_NAND 0 #define BM_GPIOMON_CTRL_OEN_NAND 0x1 #define BF_GPIOMON_CTRL_OEN_NAND(v) (((v) & 0x1) << 0) #define BFM_GPIOMON_CTRL_OEN_NAND(v) BM_GPIOMON_CTRL_OEN_NAND #define BF_GPIOMON_CTRL_OEN_NAND_V(e) BF_GPIOMON_CTRL_OEN_NAND(BV_GPIOMON_CTRL_OEN_NAND__##e) #define BFM_GPIOMON_CTRL_OEN_NAND_V(v) BM_GPIOMON_CTRL_OEN_NAND #define HW_GPIOMON_ALT1_PINMUX_BANK0 HW(GPIOMON_ALT1_PINMUX_BANK0) #define HWA_GPIOMON_ALT1_PINMUX_BANK0 (0x8003c300 + 0xd0) #define HWT_GPIOMON_ALT1_PINMUX_BANK0 HWIO_32_RW #define HWN_GPIOMON_ALT1_PINMUX_BANK0 GPIOMON_ALT1_PINMUX_BANK0 #define HWI_GPIOMON_ALT1_PINMUX_BANK0 #define HW_GPIOMON_ALT1_PINMUX_BANK0_SET HW(GPIOMON_ALT1_PINMUX_BANK0_SET) #define HWA_GPIOMON_ALT1_PINMUX_BANK0_SET (HWA_GPIOMON_ALT1_PINMUX_BANK0 + 0x4) #define HWT_GPIOMON_ALT1_PINMUX_BANK0_SET HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK0_SET GPIOMON_ALT1_PINMUX_BANK0 #define HWI_GPIOMON_ALT1_PINMUX_BANK0_SET #define HW_GPIOMON_ALT1_PINMUX_BANK0_CLR HW(GPIOMON_ALT1_PINMUX_BANK0_CLR) #define HWA_GPIOMON_ALT1_PINMUX_BANK0_CLR (HWA_GPIOMON_ALT1_PINMUX_BANK0 + 0x8) #define HWT_GPIOMON_ALT1_PINMUX_BANK0_CLR HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK0_CLR GPIOMON_ALT1_PINMUX_BANK0 #define HWI_GPIOMON_ALT1_PINMUX_BANK0_CLR #define HW_GPIOMON_ALT1_PINMUX_BANK0_TOG HW(GPIOMON_ALT1_PINMUX_BANK0_TOG) #define HWA_GPIOMON_ALT1_PINMUX_BANK0_TOG (HWA_GPIOMON_ALT1_PINMUX_BANK0 + 0xc) #define HWT_GPIOMON_ALT1_PINMUX_BANK0_TOG HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK0_TOG GPIOMON_ALT1_PINMUX_BANK0 #define HWI_GPIOMON_ALT1_PINMUX_BANK0_TOG #define BP_GPIOMON_ALT1_PINMUX_BANK0_INDEX 0 #define BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX 0xffffffff #define BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT1_PINMUX_BANK0_INDEX(v) BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX #define BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX_V(e) BF_GPIOMON_ALT1_PINMUX_BANK0_INDEX(BV_GPIOMON_ALT1_PINMUX_BANK0_INDEX__##e) #define BFM_GPIOMON_ALT1_PINMUX_BANK0_INDEX_V(v) BM_GPIOMON_ALT1_PINMUX_BANK0_INDEX #define HW_GPIOMON_ALT1_PINMUX_BANK1 HW(GPIOMON_ALT1_PINMUX_BANK1) #define HWA_GPIOMON_ALT1_PINMUX_BANK1 (0x8003c300 + 0xe0) #define HWT_GPIOMON_ALT1_PINMUX_BANK1 HWIO_32_RW #define HWN_GPIOMON_ALT1_PINMUX_BANK1 GPIOMON_ALT1_PINMUX_BANK1 #define HWI_GPIOMON_ALT1_PINMUX_BANK1 #define HW_GPIOMON_ALT1_PINMUX_BANK1_SET HW(GPIOMON_ALT1_PINMUX_BANK1_SET) #define HWA_GPIOMON_ALT1_PINMUX_BANK1_SET (HWA_GPIOMON_ALT1_PINMUX_BANK1 + 0x4) #define HWT_GPIOMON_ALT1_PINMUX_BANK1_SET HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK1_SET GPIOMON_ALT1_PINMUX_BANK1 #define HWI_GPIOMON_ALT1_PINMUX_BANK1_SET #define HW_GPIOMON_ALT1_PINMUX_BANK1_CLR HW(GPIOMON_ALT1_PINMUX_BANK1_CLR) #define HWA_GPIOMON_ALT1_PINMUX_BANK1_CLR (HWA_GPIOMON_ALT1_PINMUX_BANK1 + 0x8) #define HWT_GPIOMON_ALT1_PINMUX_BANK1_CLR HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK1_CLR GPIOMON_ALT1_PINMUX_BANK1 #define HWI_GPIOMON_ALT1_PINMUX_BANK1_CLR #define HW_GPIOMON_ALT1_PINMUX_BANK1_TOG HW(GPIOMON_ALT1_PINMUX_BANK1_TOG) #define HWA_GPIOMON_ALT1_PINMUX_BANK1_TOG (HWA_GPIOMON_ALT1_PINMUX_BANK1 + 0xc) #define HWT_GPIOMON_ALT1_PINMUX_BANK1_TOG HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK1_TOG GPIOMON_ALT1_PINMUX_BANK1 #define HWI_GPIOMON_ALT1_PINMUX_BANK1_TOG #define BP_GPIOMON_ALT1_PINMUX_BANK1_INDEX 0 #define BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX 0xffffffff #define BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT1_PINMUX_BANK1_INDEX(v) BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX #define BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX_V(e) BF_GPIOMON_ALT1_PINMUX_BANK1_INDEX(BV_GPIOMON_ALT1_PINMUX_BANK1_INDEX__##e) #define BFM_GPIOMON_ALT1_PINMUX_BANK1_INDEX_V(v) BM_GPIOMON_ALT1_PINMUX_BANK1_INDEX #define HW_GPIOMON_ALT1_PINMUX_BANK2 HW(GPIOMON_ALT1_PINMUX_BANK2) #define HWA_GPIOMON_ALT1_PINMUX_BANK2 (0x8003c300 + 0xf0) #define HWT_GPIOMON_ALT1_PINMUX_BANK2 HWIO_32_RW #define HWN_GPIOMON_ALT1_PINMUX_BANK2 GPIOMON_ALT1_PINMUX_BANK2 #define HWI_GPIOMON_ALT1_PINMUX_BANK2 #define HW_GPIOMON_ALT1_PINMUX_BANK2_SET HW(GPIOMON_ALT1_PINMUX_BANK2_SET) #define HWA_GPIOMON_ALT1_PINMUX_BANK2_SET (HWA_GPIOMON_ALT1_PINMUX_BANK2 + 0x4) #define HWT_GPIOMON_ALT1_PINMUX_BANK2_SET HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK2_SET GPIOMON_ALT1_PINMUX_BANK2 #define HWI_GPIOMON_ALT1_PINMUX_BANK2_SET #define HW_GPIOMON_ALT1_PINMUX_BANK2_CLR HW(GPIOMON_ALT1_PINMUX_BANK2_CLR) #define HWA_GPIOMON_ALT1_PINMUX_BANK2_CLR (HWA_GPIOMON_ALT1_PINMUX_BANK2 + 0x8) #define HWT_GPIOMON_ALT1_PINMUX_BANK2_CLR HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK2_CLR GPIOMON_ALT1_PINMUX_BANK2 #define HWI_GPIOMON_ALT1_PINMUX_BANK2_CLR #define HW_GPIOMON_ALT1_PINMUX_BANK2_TOG HW(GPIOMON_ALT1_PINMUX_BANK2_TOG) #define HWA_GPIOMON_ALT1_PINMUX_BANK2_TOG (HWA_GPIOMON_ALT1_PINMUX_BANK2 + 0xc) #define HWT_GPIOMON_ALT1_PINMUX_BANK2_TOG HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK2_TOG GPIOMON_ALT1_PINMUX_BANK2 #define HWI_GPIOMON_ALT1_PINMUX_BANK2_TOG #define BP_GPIOMON_ALT1_PINMUX_BANK2_INDEX 0 #define BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX 0xffffffff #define BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT1_PINMUX_BANK2_INDEX(v) BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX #define BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX_V(e) BF_GPIOMON_ALT1_PINMUX_BANK2_INDEX(BV_GPIOMON_ALT1_PINMUX_BANK2_INDEX__##e) #define BFM_GPIOMON_ALT1_PINMUX_BANK2_INDEX_V(v) BM_GPIOMON_ALT1_PINMUX_BANK2_INDEX #define HW_GPIOMON_ALT1_PINMUX_BANK3 HW(GPIOMON_ALT1_PINMUX_BANK3) #define HWA_GPIOMON_ALT1_PINMUX_BANK3 (0x8003c300 + 0x100) #define HWT_GPIOMON_ALT1_PINMUX_BANK3 HWIO_32_RW #define HWN_GPIOMON_ALT1_PINMUX_BANK3 GPIOMON_ALT1_PINMUX_BANK3 #define HWI_GPIOMON_ALT1_PINMUX_BANK3 #define HW_GPIOMON_ALT1_PINMUX_BANK3_SET HW(GPIOMON_ALT1_PINMUX_BANK3_SET) #define HWA_GPIOMON_ALT1_PINMUX_BANK3_SET (HWA_GPIOMON_ALT1_PINMUX_BANK3 + 0x4) #define HWT_GPIOMON_ALT1_PINMUX_BANK3_SET HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK3_SET GPIOMON_ALT1_PINMUX_BANK3 #define HWI_GPIOMON_ALT1_PINMUX_BANK3_SET #define HW_GPIOMON_ALT1_PINMUX_BANK3_CLR HW(GPIOMON_ALT1_PINMUX_BANK3_CLR) #define HWA_GPIOMON_ALT1_PINMUX_BANK3_CLR (HWA_GPIOMON_ALT1_PINMUX_BANK3 + 0x8) #define HWT_GPIOMON_ALT1_PINMUX_BANK3_CLR HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK3_CLR GPIOMON_ALT1_PINMUX_BANK3 #define HWI_GPIOMON_ALT1_PINMUX_BANK3_CLR #define HW_GPIOMON_ALT1_PINMUX_BANK3_TOG HW(GPIOMON_ALT1_PINMUX_BANK3_TOG) #define HWA_GPIOMON_ALT1_PINMUX_BANK3_TOG (HWA_GPIOMON_ALT1_PINMUX_BANK3 + 0xc) #define HWT_GPIOMON_ALT1_PINMUX_BANK3_TOG HWIO_32_WO #define HWN_GPIOMON_ALT1_PINMUX_BANK3_TOG GPIOMON_ALT1_PINMUX_BANK3 #define HWI_GPIOMON_ALT1_PINMUX_BANK3_TOG #define BP_GPIOMON_ALT1_PINMUX_BANK3_INDEX 0 #define BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX 0xffffffff #define BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT1_PINMUX_BANK3_INDEX(v) BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX #define BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX_V(e) BF_GPIOMON_ALT1_PINMUX_BANK3_INDEX(BV_GPIOMON_ALT1_PINMUX_BANK3_INDEX__##e) #define BFM_GPIOMON_ALT1_PINMUX_BANK3_INDEX_V(v) BM_GPIOMON_ALT1_PINMUX_BANK3_INDEX #define HW_GPIOMON_ALT2_PINMUX_BANK0 HW(GPIOMON_ALT2_PINMUX_BANK0) #define HWA_GPIOMON_ALT2_PINMUX_BANK0 (0x8003c300 + 0x110) #define HWT_GPIOMON_ALT2_PINMUX_BANK0 HWIO_32_RW #define HWN_GPIOMON_ALT2_PINMUX_BANK0 GPIOMON_ALT2_PINMUX_BANK0 #define HWI_GPIOMON_ALT2_PINMUX_BANK0 #define HW_GPIOMON_ALT2_PINMUX_BANK0_SET HW(GPIOMON_ALT2_PINMUX_BANK0_SET) #define HWA_GPIOMON_ALT2_PINMUX_BANK0_SET (HWA_GPIOMON_ALT2_PINMUX_BANK0 + 0x4) #define HWT_GPIOMON_ALT2_PINMUX_BANK0_SET HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK0_SET GPIOMON_ALT2_PINMUX_BANK0 #define HWI_GPIOMON_ALT2_PINMUX_BANK0_SET #define HW_GPIOMON_ALT2_PINMUX_BANK0_CLR HW(GPIOMON_ALT2_PINMUX_BANK0_CLR) #define HWA_GPIOMON_ALT2_PINMUX_BANK0_CLR (HWA_GPIOMON_ALT2_PINMUX_BANK0 + 0x8) #define HWT_GPIOMON_ALT2_PINMUX_BANK0_CLR HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK0_CLR GPIOMON_ALT2_PINMUX_BANK0 #define HWI_GPIOMON_ALT2_PINMUX_BANK0_CLR #define HW_GPIOMON_ALT2_PINMUX_BANK0_TOG HW(GPIOMON_ALT2_PINMUX_BANK0_TOG) #define HWA_GPIOMON_ALT2_PINMUX_BANK0_TOG (HWA_GPIOMON_ALT2_PINMUX_BANK0 + 0xc) #define HWT_GPIOMON_ALT2_PINMUX_BANK0_TOG HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK0_TOG GPIOMON_ALT2_PINMUX_BANK0 #define HWI_GPIOMON_ALT2_PINMUX_BANK0_TOG #define BP_GPIOMON_ALT2_PINMUX_BANK0_INDEX 0 #define BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX 0xffffffff #define BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT2_PINMUX_BANK0_INDEX(v) BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX #define BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX_V(e) BF_GPIOMON_ALT2_PINMUX_BANK0_INDEX(BV_GPIOMON_ALT2_PINMUX_BANK0_INDEX__##e) #define BFM_GPIOMON_ALT2_PINMUX_BANK0_INDEX_V(v) BM_GPIOMON_ALT2_PINMUX_BANK0_INDEX #define HW_GPIOMON_ALT2_PINMUX_BANK1 HW(GPIOMON_ALT2_PINMUX_BANK1) #define HWA_GPIOMON_ALT2_PINMUX_BANK1 (0x8003c300 + 0x120) #define HWT_GPIOMON_ALT2_PINMUX_BANK1 HWIO_32_RW #define HWN_GPIOMON_ALT2_PINMUX_BANK1 GPIOMON_ALT2_PINMUX_BANK1 #define HWI_GPIOMON_ALT2_PINMUX_BANK1 #define HW_GPIOMON_ALT2_PINMUX_BANK1_SET HW(GPIOMON_ALT2_PINMUX_BANK1_SET) #define HWA_GPIOMON_ALT2_PINMUX_BANK1_SET (HWA_GPIOMON_ALT2_PINMUX_BANK1 + 0x4) #define HWT_GPIOMON_ALT2_PINMUX_BANK1_SET HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK1_SET GPIOMON_ALT2_PINMUX_BANK1 #define HWI_GPIOMON_ALT2_PINMUX_BANK1_SET #define HW_GPIOMON_ALT2_PINMUX_BANK1_CLR HW(GPIOMON_ALT2_PINMUX_BANK1_CLR) #define HWA_GPIOMON_ALT2_PINMUX_BANK1_CLR (HWA_GPIOMON_ALT2_PINMUX_BANK1 + 0x8) #define HWT_GPIOMON_ALT2_PINMUX_BANK1_CLR HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK1_CLR GPIOMON_ALT2_PINMUX_BANK1 #define HWI_GPIOMON_ALT2_PINMUX_BANK1_CLR #define HW_GPIOMON_ALT2_PINMUX_BANK1_TOG HW(GPIOMON_ALT2_PINMUX_BANK1_TOG) #define HWA_GPIOMON_ALT2_PINMUX_BANK1_TOG (HWA_GPIOMON_ALT2_PINMUX_BANK1 + 0xc) #define HWT_GPIOMON_ALT2_PINMUX_BANK1_TOG HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK1_TOG GPIOMON_ALT2_PINMUX_BANK1 #define HWI_GPIOMON_ALT2_PINMUX_BANK1_TOG #define BP_GPIOMON_ALT2_PINMUX_BANK1_INDEX 0 #define BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX 0xffffffff #define BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT2_PINMUX_BANK1_INDEX(v) BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX #define BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX_V(e) BF_GPIOMON_ALT2_PINMUX_BANK1_INDEX(BV_GPIOMON_ALT2_PINMUX_BANK1_INDEX__##e) #define BFM_GPIOMON_ALT2_PINMUX_BANK1_INDEX_V(v) BM_GPIOMON_ALT2_PINMUX_BANK1_INDEX #define HW_GPIOMON_ALT2_PINMUX_BANK2 HW(GPIOMON_ALT2_PINMUX_BANK2) #define HWA_GPIOMON_ALT2_PINMUX_BANK2 (0x8003c300 + 0x130) #define HWT_GPIOMON_ALT2_PINMUX_BANK2 HWIO_32_RW #define HWN_GPIOMON_ALT2_PINMUX_BANK2 GPIOMON_ALT2_PINMUX_BANK2 #define HWI_GPIOMON_ALT2_PINMUX_BANK2 #define HW_GPIOMON_ALT2_PINMUX_BANK2_SET HW(GPIOMON_ALT2_PINMUX_BANK2_SET) #define HWA_GPIOMON_ALT2_PINMUX_BANK2_SET (HWA_GPIOMON_ALT2_PINMUX_BANK2 + 0x4) #define HWT_GPIOMON_ALT2_PINMUX_BANK2_SET HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK2_SET GPIOMON_ALT2_PINMUX_BANK2 #define HWI_GPIOMON_ALT2_PINMUX_BANK2_SET #define HW_GPIOMON_ALT2_PINMUX_BANK2_CLR HW(GPIOMON_ALT2_PINMUX_BANK2_CLR) #define HWA_GPIOMON_ALT2_PINMUX_BANK2_CLR (HWA_GPIOMON_ALT2_PINMUX_BANK2 + 0x8) #define HWT_GPIOMON_ALT2_PINMUX_BANK2_CLR HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK2_CLR GPIOMON_ALT2_PINMUX_BANK2 #define HWI_GPIOMON_ALT2_PINMUX_BANK2_CLR #define HW_GPIOMON_ALT2_PINMUX_BANK2_TOG HW(GPIOMON_ALT2_PINMUX_BANK2_TOG) #define HWA_GPIOMON_ALT2_PINMUX_BANK2_TOG (HWA_GPIOMON_ALT2_PINMUX_BANK2 + 0xc) #define HWT_GPIOMON_ALT2_PINMUX_BANK2_TOG HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK2_TOG GPIOMON_ALT2_PINMUX_BANK2 #define HWI_GPIOMON_ALT2_PINMUX_BANK2_TOG #define BP_GPIOMON_ALT2_PINMUX_BANK2_INDEX 0 #define BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX 0xffffffff #define BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT2_PINMUX_BANK2_INDEX(v) BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX #define BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX_V(e) BF_GPIOMON_ALT2_PINMUX_BANK2_INDEX(BV_GPIOMON_ALT2_PINMUX_BANK2_INDEX__##e) #define BFM_GPIOMON_ALT2_PINMUX_BANK2_INDEX_V(v) BM_GPIOMON_ALT2_PINMUX_BANK2_INDEX #define HW_GPIOMON_ALT2_PINMUX_BANK3 HW(GPIOMON_ALT2_PINMUX_BANK3) #define HWA_GPIOMON_ALT2_PINMUX_BANK3 (0x8003c300 + 0x140) #define HWT_GPIOMON_ALT2_PINMUX_BANK3 HWIO_32_RW #define HWN_GPIOMON_ALT2_PINMUX_BANK3 GPIOMON_ALT2_PINMUX_BANK3 #define HWI_GPIOMON_ALT2_PINMUX_BANK3 #define HW_GPIOMON_ALT2_PINMUX_BANK3_SET HW(GPIOMON_ALT2_PINMUX_BANK3_SET) #define HWA_GPIOMON_ALT2_PINMUX_BANK3_SET (HWA_GPIOMON_ALT2_PINMUX_BANK3 + 0x4) #define HWT_GPIOMON_ALT2_PINMUX_BANK3_SET HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK3_SET GPIOMON_ALT2_PINMUX_BANK3 #define HWI_GPIOMON_ALT2_PINMUX_BANK3_SET #define HW_GPIOMON_ALT2_PINMUX_BANK3_CLR HW(GPIOMON_ALT2_PINMUX_BANK3_CLR) #define HWA_GPIOMON_ALT2_PINMUX_BANK3_CLR (HWA_GPIOMON_ALT2_PINMUX_BANK3 + 0x8) #define HWT_GPIOMON_ALT2_PINMUX_BANK3_CLR HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK3_CLR GPIOMON_ALT2_PINMUX_BANK3 #define HWI_GPIOMON_ALT2_PINMUX_BANK3_CLR #define HW_GPIOMON_ALT2_PINMUX_BANK3_TOG HW(GPIOMON_ALT2_PINMUX_BANK3_TOG) #define HWA_GPIOMON_ALT2_PINMUX_BANK3_TOG (HWA_GPIOMON_ALT2_PINMUX_BANK3 + 0xc) #define HWT_GPIOMON_ALT2_PINMUX_BANK3_TOG HWIO_32_WO #define HWN_GPIOMON_ALT2_PINMUX_BANK3_TOG GPIOMON_ALT2_PINMUX_BANK3 #define HWI_GPIOMON_ALT2_PINMUX_BANK3_TOG #define BP_GPIOMON_ALT2_PINMUX_BANK3_INDEX 0 #define BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX 0xffffffff #define BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT2_PINMUX_BANK3_INDEX(v) BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX #define BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX_V(e) BF_GPIOMON_ALT2_PINMUX_BANK3_INDEX(BV_GPIOMON_ALT2_PINMUX_BANK3_INDEX__##e) #define BFM_GPIOMON_ALT2_PINMUX_BANK3_INDEX_V(v) BM_GPIOMON_ALT2_PINMUX_BANK3_INDEX #define HW_GPIOMON_ALT3_PINMUX_BANK0 HW(GPIOMON_ALT3_PINMUX_BANK0) #define HWA_GPIOMON_ALT3_PINMUX_BANK0 (0x8003c300 + 0x150) #define HWT_GPIOMON_ALT3_PINMUX_BANK0 HWIO_32_RW #define HWN_GPIOMON_ALT3_PINMUX_BANK0 GPIOMON_ALT3_PINMUX_BANK0 #define HWI_GPIOMON_ALT3_PINMUX_BANK0 #define HW_GPIOMON_ALT3_PINMUX_BANK0_SET HW(GPIOMON_ALT3_PINMUX_BANK0_SET) #define HWA_GPIOMON_ALT3_PINMUX_BANK0_SET (HWA_GPIOMON_ALT3_PINMUX_BANK0 + 0x4) #define HWT_GPIOMON_ALT3_PINMUX_BANK0_SET HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK0_SET GPIOMON_ALT3_PINMUX_BANK0 #define HWI_GPIOMON_ALT3_PINMUX_BANK0_SET #define HW_GPIOMON_ALT3_PINMUX_BANK0_CLR HW(GPIOMON_ALT3_PINMUX_BANK0_CLR) #define HWA_GPIOMON_ALT3_PINMUX_BANK0_CLR (HWA_GPIOMON_ALT3_PINMUX_BANK0 + 0x8) #define HWT_GPIOMON_ALT3_PINMUX_BANK0_CLR HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK0_CLR GPIOMON_ALT3_PINMUX_BANK0 #define HWI_GPIOMON_ALT3_PINMUX_BANK0_CLR #define HW_GPIOMON_ALT3_PINMUX_BANK0_TOG HW(GPIOMON_ALT3_PINMUX_BANK0_TOG) #define HWA_GPIOMON_ALT3_PINMUX_BANK0_TOG (HWA_GPIOMON_ALT3_PINMUX_BANK0 + 0xc) #define HWT_GPIOMON_ALT3_PINMUX_BANK0_TOG HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK0_TOG GPIOMON_ALT3_PINMUX_BANK0 #define HWI_GPIOMON_ALT3_PINMUX_BANK0_TOG #define BP_GPIOMON_ALT3_PINMUX_BANK0_INDEX 0 #define BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX 0xffffffff #define BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT3_PINMUX_BANK0_INDEX(v) BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX #define BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX_V(e) BF_GPIOMON_ALT3_PINMUX_BANK0_INDEX(BV_GPIOMON_ALT3_PINMUX_BANK0_INDEX__##e) #define BFM_GPIOMON_ALT3_PINMUX_BANK0_INDEX_V(v) BM_GPIOMON_ALT3_PINMUX_BANK0_INDEX #define HW_GPIOMON_ALT3_PINMUX_BANK1 HW(GPIOMON_ALT3_PINMUX_BANK1) #define HWA_GPIOMON_ALT3_PINMUX_BANK1 (0x8003c300 + 0x160) #define HWT_GPIOMON_ALT3_PINMUX_BANK1 HWIO_32_RW #define HWN_GPIOMON_ALT3_PINMUX_BANK1 GPIOMON_ALT3_PINMUX_BANK1 #define HWI_GPIOMON_ALT3_PINMUX_BANK1 #define HW_GPIOMON_ALT3_PINMUX_BANK1_SET HW(GPIOMON_ALT3_PINMUX_BANK1_SET) #define HWA_GPIOMON_ALT3_PINMUX_BANK1_SET (HWA_GPIOMON_ALT3_PINMUX_BANK1 + 0x4) #define HWT_GPIOMON_ALT3_PINMUX_BANK1_SET HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK1_SET GPIOMON_ALT3_PINMUX_BANK1 #define HWI_GPIOMON_ALT3_PINMUX_BANK1_SET #define HW_GPIOMON_ALT3_PINMUX_BANK1_CLR HW(GPIOMON_ALT3_PINMUX_BANK1_CLR) #define HWA_GPIOMON_ALT3_PINMUX_BANK1_CLR (HWA_GPIOMON_ALT3_PINMUX_BANK1 + 0x8) #define HWT_GPIOMON_ALT3_PINMUX_BANK1_CLR HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK1_CLR GPIOMON_ALT3_PINMUX_BANK1 #define HWI_GPIOMON_ALT3_PINMUX_BANK1_CLR #define HW_GPIOMON_ALT3_PINMUX_BANK1_TOG HW(GPIOMON_ALT3_PINMUX_BANK1_TOG) #define HWA_GPIOMON_ALT3_PINMUX_BANK1_TOG (HWA_GPIOMON_ALT3_PINMUX_BANK1 + 0xc) #define HWT_GPIOMON_ALT3_PINMUX_BANK1_TOG HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK1_TOG GPIOMON_ALT3_PINMUX_BANK1 #define HWI_GPIOMON_ALT3_PINMUX_BANK1_TOG #define BP_GPIOMON_ALT3_PINMUX_BANK1_INDEX 0 #define BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX 0xffffffff #define BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT3_PINMUX_BANK1_INDEX(v) BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX #define BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX_V(e) BF_GPIOMON_ALT3_PINMUX_BANK1_INDEX(BV_GPIOMON_ALT3_PINMUX_BANK1_INDEX__##e) #define BFM_GPIOMON_ALT3_PINMUX_BANK1_INDEX_V(v) BM_GPIOMON_ALT3_PINMUX_BANK1_INDEX #define HW_GPIOMON_ALT3_PINMUX_BANK2 HW(GPIOMON_ALT3_PINMUX_BANK2) #define HWA_GPIOMON_ALT3_PINMUX_BANK2 (0x8003c300 + 0x170) #define HWT_GPIOMON_ALT3_PINMUX_BANK2 HWIO_32_RW #define HWN_GPIOMON_ALT3_PINMUX_BANK2 GPIOMON_ALT3_PINMUX_BANK2 #define HWI_GPIOMON_ALT3_PINMUX_BANK2 #define HW_GPIOMON_ALT3_PINMUX_BANK2_SET HW(GPIOMON_ALT3_PINMUX_BANK2_SET) #define HWA_GPIOMON_ALT3_PINMUX_BANK2_SET (HWA_GPIOMON_ALT3_PINMUX_BANK2 + 0x4) #define HWT_GPIOMON_ALT3_PINMUX_BANK2_SET HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK2_SET GPIOMON_ALT3_PINMUX_BANK2 #define HWI_GPIOMON_ALT3_PINMUX_BANK2_SET #define HW_GPIOMON_ALT3_PINMUX_BANK2_CLR HW(GPIOMON_ALT3_PINMUX_BANK2_CLR) #define HWA_GPIOMON_ALT3_PINMUX_BANK2_CLR (HWA_GPIOMON_ALT3_PINMUX_BANK2 + 0x8) #define HWT_GPIOMON_ALT3_PINMUX_BANK2_CLR HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK2_CLR GPIOMON_ALT3_PINMUX_BANK2 #define HWI_GPIOMON_ALT3_PINMUX_BANK2_CLR #define HW_GPIOMON_ALT3_PINMUX_BANK2_TOG HW(GPIOMON_ALT3_PINMUX_BANK2_TOG) #define HWA_GPIOMON_ALT3_PINMUX_BANK2_TOG (HWA_GPIOMON_ALT3_PINMUX_BANK2 + 0xc) #define HWT_GPIOMON_ALT3_PINMUX_BANK2_TOG HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK2_TOG GPIOMON_ALT3_PINMUX_BANK2 #define HWI_GPIOMON_ALT3_PINMUX_BANK2_TOG #define BP_GPIOMON_ALT3_PINMUX_BANK2_INDEX 0 #define BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX 0xffffffff #define BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT3_PINMUX_BANK2_INDEX(v) BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX #define BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX_V(e) BF_GPIOMON_ALT3_PINMUX_BANK2_INDEX(BV_GPIOMON_ALT3_PINMUX_BANK2_INDEX__##e) #define BFM_GPIOMON_ALT3_PINMUX_BANK2_INDEX_V(v) BM_GPIOMON_ALT3_PINMUX_BANK2_INDEX #define HW_GPIOMON_ALT3_PINMUX_BANK3 HW(GPIOMON_ALT3_PINMUX_BANK3) #define HWA_GPIOMON_ALT3_PINMUX_BANK3 (0x8003c300 + 0x180) #define HWT_GPIOMON_ALT3_PINMUX_BANK3 HWIO_32_RW #define HWN_GPIOMON_ALT3_PINMUX_BANK3 GPIOMON_ALT3_PINMUX_BANK3 #define HWI_GPIOMON_ALT3_PINMUX_BANK3 #define HW_GPIOMON_ALT3_PINMUX_BANK3_SET HW(GPIOMON_ALT3_PINMUX_BANK3_SET) #define HWA_GPIOMON_ALT3_PINMUX_BANK3_SET (HWA_GPIOMON_ALT3_PINMUX_BANK3 + 0x4) #define HWT_GPIOMON_ALT3_PINMUX_BANK3_SET HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK3_SET GPIOMON_ALT3_PINMUX_BANK3 #define HWI_GPIOMON_ALT3_PINMUX_BANK3_SET #define HW_GPIOMON_ALT3_PINMUX_BANK3_CLR HW(GPIOMON_ALT3_PINMUX_BANK3_CLR) #define HWA_GPIOMON_ALT3_PINMUX_BANK3_CLR (HWA_GPIOMON_ALT3_PINMUX_BANK3 + 0x8) #define HWT_GPIOMON_ALT3_PINMUX_BANK3_CLR HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK3_CLR GPIOMON_ALT3_PINMUX_BANK3 #define HWI_GPIOMON_ALT3_PINMUX_BANK3_CLR #define HW_GPIOMON_ALT3_PINMUX_BANK3_TOG HW(GPIOMON_ALT3_PINMUX_BANK3_TOG) #define HWA_GPIOMON_ALT3_PINMUX_BANK3_TOG (HWA_GPIOMON_ALT3_PINMUX_BANK3 + 0xc) #define HWT_GPIOMON_ALT3_PINMUX_BANK3_TOG HWIO_32_WO #define HWN_GPIOMON_ALT3_PINMUX_BANK3_TOG GPIOMON_ALT3_PINMUX_BANK3 #define HWI_GPIOMON_ALT3_PINMUX_BANK3_TOG #define BP_GPIOMON_ALT3_PINMUX_BANK3_INDEX 0 #define BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX 0xffffffff #define BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX(v) (((v) & 0xffffffff) << 0) #define BFM_GPIOMON_ALT3_PINMUX_BANK3_INDEX(v) BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX #define BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX_V(e) BF_GPIOMON_ALT3_PINMUX_BANK3_INDEX(BV_GPIOMON_ALT3_PINMUX_BANK3_INDEX__##e) #define BFM_GPIOMON_ALT3_PINMUX_BANK3_INDEX_V(v) BM_GPIOMON_ALT3_PINMUX_BANK3_INDEX #endif /* __HEADERGEN_STMP3700_GPIOMON_H__*/