/*************************************************************************** * __________ __ ___. * Open \______ \ ____ ____ | | _\_ |__ _______ ___ * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ * \/ \/ \/ \/ \/ * This file was automatically generated by headergen, DO NOT EDIT it. * headergen version: 3.0.0 * x1000 version: 1.0 * x1000 authors: Aidan MacDonald * * Copyright (C) 2015 by the authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation; either version 2 * of the License, or (at your option) any later version. * * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY * KIND, either express or implied. * ****************************************************************************/ #ifndef __HEADERGEN_AIC_H__ #define __HEADERGEN_AIC_H__ #include "macro.h" #define REG_AIC_CFG jz_reg(AIC_CFG) #define JA_AIC_CFG (0xb0020000 + 0x0) #define JT_AIC_CFG JIO_32_RW #define JN_AIC_CFG AIC_CFG #define JI_AIC_CFG #define BP_AIC_CFG_RFTH 24 #define BM_AIC_CFG_RFTH 0xf000000 #define BF_AIC_CFG_RFTH(v) (((v) & 0xf) << 24) #define BFM_AIC_CFG_RFTH(v) BM_AIC_CFG_RFTH #define BF_AIC_CFG_RFTH_V(e) BF_AIC_CFG_RFTH(BV_AIC_CFG_RFTH__##e) #define BFM_AIC_CFG_RFTH_V(v) BM_AIC_CFG_RFTH #define BP_AIC_CFG_TFTH 16 #define BM_AIC_CFG_TFTH 0x1f0000 #define BF_AIC_CFG_TFTH(v) (((v) & 0x1f) << 16) #define BFM_AIC_CFG_TFTH(v) BM_AIC_CFG_TFTH #define BF_AIC_CFG_TFTH_V(e) BF_AIC_CFG_TFTH(BV_AIC_CFG_TFTH__##e) #define BFM_AIC_CFG_TFTH_V(v) BM_AIC_CFG_TFTH #define BP_AIC_CFG_MSB 12 #define BM_AIC_CFG_MSB 0x1000 #define BF_AIC_CFG_MSB(v) (((v) & 0x1) << 12) #define BFM_AIC_CFG_MSB(v) BM_AIC_CFG_MSB #define BF_AIC_CFG_MSB_V(e) BF_AIC_CFG_MSB(BV_AIC_CFG_MSB__##e) #define BFM_AIC_CFG_MSB_V(v) BM_AIC_CFG_MSB #define BP_AIC_CFG_IBCKD 10 #define BM_AIC_CFG_IBCKD 0x400 #define BF_AIC_CFG_IBCKD(v) (((v) & 0x1) << 10) #define BFM_AIC_CFG_IBCKD(v) BM_AIC_CFG_IBCKD #define BF_AIC_CFG_IBCKD_V(e) BF_AIC_CFG_IBCKD(BV_AIC_CFG_IBCKD__##e) #define BFM_AIC_CFG_IBCKD_V(v) BM_AIC_CFG_IBCKD #define BP_AIC_CFG_ISYNCD 9 #define BM_AIC_CFG_ISYNCD 0x200 #define BF_AIC_CFG_ISYNCD(v) (((v) & 0x1) << 9) #define BFM_AIC_CFG_ISYNCD(v) BM_AIC_CFG_ISYNCD #define BF_AIC_CFG_ISYNCD_V(e) BF_AIC_CFG_ISYNCD(BV_AIC_CFG_ISYNCD__##e) #define BFM_AIC_CFG_ISYNCD_V(v) BM_AIC_CFG_ISYNCD #define BP_AIC_CFG_DMODE 8 #define BM_AIC_CFG_DMODE 0x100 #define BF_AIC_CFG_DMODE(v) (((v) & 0x1) << 8) #define BFM_AIC_CFG_DMODE(v) BM_AIC_CFG_DMODE #define BF_AIC_CFG_DMODE_V(e) BF_AIC_CFG_DMODE(BV_AIC_CFG_DMODE__##e) #define BFM_AIC_CFG_DMODE_V(v) BM_AIC_CFG_DMODE #define BP_AIC_CFG_CDC_SLAVE 7 #define BM_AIC_CFG_CDC_SLAVE 0x80 #define BF_AIC_CFG_CDC_SLAVE(v) (((v) & 0x1) << 7) #define BFM_AIC_CFG_CDC_SLAVE(v) BM_AIC_CFG_CDC_SLAVE #define BF_AIC_CFG_CDC_SLAVE_V(e) BF_AIC_CFG_CDC_SLAVE(BV_AIC_CFG_CDC_SLAVE__##e) #define BFM_AIC_CFG_CDC_SLAVE_V(v) BM_AIC_CFG_CDC_SLAVE #define BP_AIC_CFG_LSMP 6 #define BM_AIC_CFG_LSMP 0x40 #define BF_AIC_CFG_LSMP(v) (((v) & 0x1) << 6) #define BFM_AIC_CFG_LSMP(v) BM_AIC_CFG_LSMP #define BF_AIC_CFG_LSMP_V(e) BF_AIC_CFG_LSMP(BV_AIC_CFG_LSMP__##e) #define BFM_AIC_CFG_LSMP_V(v) BM_AIC_CFG_LSMP #define BP_AIC_CFG_ICDC 5 #define BM_AIC_CFG_ICDC 0x20 #define BF_AIC_CFG_ICDC(v) (((v) & 0x1) << 5) #define BFM_AIC_CFG_ICDC(v) BM_AIC_CFG_ICDC #define BF_AIC_CFG_ICDC_V(e) BF_AIC_CFG_ICDC(BV_AIC_CFG_ICDC__##e) #define BFM_AIC_CFG_ICDC_V(v) BM_AIC_CFG_ICDC #define BP_AIC_CFG_AUSEL 4 #define BM_AIC_CFG_AUSEL 0x10 #define BF_AIC_CFG_AUSEL(v) (((v) & 0x1) << 4) #define BFM_AIC_CFG_AUSEL(v) BM_AIC_CFG_AUSEL #define BF_AIC_CFG_AUSEL_V(e) BF_AIC_CFG_AUSEL(BV_AIC_CFG_AUSEL__##e) #define BFM_AIC_CFG_AUSEL_V(v) BM_AIC_CFG_AUSEL #define BP_AIC_CFG_RST 3 #define BM_AIC_CFG_RST 0x8 #define BF_AIC_CFG_RST(v) (((v) & 0x1) << 3) #define BFM_AIC_CFG_RST(v) BM_AIC_CFG_RST #define BF_AIC_CFG_RST_V(e) BF_AIC_CFG_RST(BV_AIC_CFG_RST__##e) #define BFM_AIC_CFG_RST_V(v) BM_AIC_CFG_RST #define BP_AIC_CFG_BCKD 2 #define BM_AIC_CFG_BCKD 0x4 #define BF_AIC_CFG_BCKD(v) (((v) & 0x1) << 2) #define BFM_AIC_CFG_BCKD(v) BM_AIC_CFG_BCKD #define BF_AIC_CFG_BCKD_V(e) BF_AIC_CFG_BCKD(BV_AIC_CFG_BCKD__##e) #define BFM_AIC_CFG_BCKD_V(v) BM_AIC_CFG_BCKD #define BP_AIC_CFG_SYNCD 1 #define BM_AIC_CFG_SYNCD 0x2 #define BF_AIC_CFG_SYNCD(v) (((v) & 0x1) << 1) #define BFM_AIC_CFG_SYNCD(v) BM_AIC_CFG_SYNCD #define BF_AIC_CFG_SYNCD_V(e) BF_AIC_CFG_SYNCD(BV_AIC_CFG_SYNCD__##e) #define BFM_AIC_CFG_SYNCD_V(v) BM_AIC_CFG_SYNCD #define BP_AIC_CFG_ENABLE 0 #define BM_AIC_CFG_ENABLE 0x1 #define BF_AIC_CFG_ENABLE(v) (((v) & 0x1) << 0) #define BFM_AIC_CFG_ENABLE(v) BM_AIC_CFG_ENABLE #define BF_AIC_CFG_ENABLE_V(e) BF_AIC_CFG_ENABLE(BV_AIC_CFG_ENABLE__##e) #define BFM_AIC_CFG_ENABLE_V(v) BM_AIC_CFG_ENABLE #define REG_AIC_CCR jz_reg(AIC_CCR) #define JA_AIC_CCR (0xb0020000 + 0x4) #define JT_AIC_CCR JIO_32_RW #define JN_AIC_CCR AIC_CCR #define JI_AIC_CCR #define BP_AIC_CCR_CHANNEL 24 #define BM_AIC_CCR_CHANNEL 0x7000000 #define BV_AIC_CCR_CHANNEL__MONO 0x0 #define BV_AIC_CCR_CHANNEL__STEREO 0x1 #define BF_AIC_CCR_CHANNEL(v) (((v) & 0x7) << 24) #define BFM_AIC_CCR_CHANNEL(v) BM_AIC_CCR_CHANNEL #define BF_AIC_CCR_CHANNEL_V(e) BF_AIC_CCR_CHANNEL(BV_AIC_CCR_CHANNEL__##e) #define BFM_AIC_CCR_CHANNEL_V(v) BM_AIC_CCR_CHANNEL #define BP_AIC_CCR_OSS 19 #define BM_AIC_CCR_OSS 0x380000 #define BV_AIC_CCR_OSS__8BIT 0x0 #define BV_AIC_CCR_OSS__16BIT 0x1 #define BV_AIC_CCR_OSS__18BIT 0x2 #define BV_AIC_CCR_OSS__20BIT 0x3 #define BV_AIC_CCR_OSS__24BIT 0x4 #define BF_AIC_CCR_OSS(v) (((v) & 0x7) << 19) #define BFM_AIC_CCR_OSS(v) BM_AIC_CCR_OSS #define BF_AIC_CCR_OSS_V(e) BF_AIC_CCR_OSS(BV_AIC_CCR_OSS__##e) #define BFM_AIC_CCR_OSS_V(v) BM_AIC_CCR_OSS #define BP_AIC_CCR_ISS 16 #define BM_AIC_CCR_ISS 0x70000 #define BV_AIC_CCR_ISS__8BIT 0x0 #define BV_AIC_CCR_ISS__16BIT 0x1 #define BV_AIC_CCR_ISS__18BIT 0x2 #define BV_AIC_CCR_ISS__20BIT 0x3 #define BV_AIC_CCR_ISS__24BIT 0x4 #define BF_AIC_CCR_ISS(v) (((v) & 0x7) << 16) #define BFM_AIC_CCR_ISS(v) BM_AIC_CCR_ISS #define BF_AIC_CCR_ISS_V(e) BF_AIC_CCR_ISS(BV_AIC_CCR_ISS__##e) #define BFM_AIC_CCR_ISS_V(v) BM_AIC_CCR_ISS #define BP_AIC_CCR_PACK16 28 #define BM_AIC_CCR_PACK16 0x10000000 #define BF_AIC_CCR_PACK16(v) (((v) & 0x1) << 28) #define BFM_AIC_CCR_PACK16(v) BM_AIC_CCR_PACK16 #define BF_AIC_CCR_PACK16_V(e) BF_AIC_CCR_PACK16(BV_AIC_CCR_PACK16__##e) #define BFM_AIC_CCR_PACK16_V(v) BM_AIC_CCR_PACK16 #define BP_AIC_CCR_RDMS 15 #define BM_AIC_CCR_RDMS 0x8000 #define BF_AIC_CCR_RDMS(v) (((v) & 0x1) << 15) #define BFM_AIC_CCR_RDMS(v) BM_AIC_CCR_RDMS #define BF_AIC_CCR_RDMS_V(e) BF_AIC_CCR_RDMS(BV_AIC_CCR_RDMS__##e) #define BFM_AIC_CCR_RDMS_V(v) BM_AIC_CCR_RDMS #define BP_AIC_CCR_TDMS 14 #define BM_AIC_CCR_TDMS 0x4000 #define BF_AIC_CCR_TDMS(v) (((v) & 0x1) << 14) #define BFM_AIC_CCR_TDMS(v) BM_AIC_CCR_TDMS #define BF_AIC_CCR_TDMS_V(e) BF_AIC_CCR_TDMS(BV_AIC_CCR_TDMS__##e) #define BFM_AIC_CCR_TDMS_V(v) BM_AIC_CCR_TDMS #define BP_AIC_CCR_M2S 11 #define BM_AIC_CCR_M2S 0x800 #define BF_AIC_CCR_M2S(v) (((v) & 0x1) << 11) #define BFM_AIC_CCR_M2S(v) BM_AIC_CCR_M2S #define BF_AIC_CCR_M2S_V(e) BF_AIC_CCR_M2S(BV_AIC_CCR_M2S__##e) #define BFM_AIC_CCR_M2S_V(v) BM_AIC_CCR_M2S #define BP_AIC_CCR_ENDSW 10 #define BM_AIC_CCR_ENDSW 0x400 #define BF_AIC_CCR_ENDSW(v) (((v) & 0x1) << 10) #define BFM_AIC_CCR_ENDSW(v) BM_AIC_CCR_ENDSW #define BF_AIC_CCR_ENDSW_V(e) BF_AIC_CCR_ENDSW(BV_AIC_CCR_ENDSW__##e) #define BFM_AIC_CCR_ENDSW_V(v) BM_AIC_CCR_ENDSW #define BP_AIC_CCR_ASVTSU 9 #define BM_AIC_CCR_ASVTSU 0x200 #define BF_AIC_CCR_ASVTSU(v) (((v) & 0x1) << 9) #define BFM_AIC_CCR_ASVTSU(v) BM_AIC_CCR_ASVTSU #define BF_AIC_CCR_ASVTSU_V(e) BF_AIC_CCR_ASVTSU(BV_AIC_CCR_ASVTSU__##e) #define BFM_AIC_CCR_ASVTSU_V(v) BM_AIC_CCR_ASVTSU #define BP_AIC_CCR_TFLUSH 8 #define BM_AIC_CCR_TFLUSH 0x100 #define BF_AIC_CCR_TFLUSH(v) (((v) & 0x1) << 8) #define BFM_AIC_CCR_TFLUSH(v) BM_AIC_CCR_TFLUSH #define BF_AIC_CCR_TFLUSH_V(e) BF_AIC_CCR_TFLUSH(BV_AIC_CCR_TFLUSH__##e) #define BFM_AIC_CCR_TFLUSH_V(v) BM_AIC_CCR_TFLUSH #define BP_AIC_CCR_RFLUSH 7 #define BM_AIC_CCR_RFLUSH 0x80 #define BF_AIC_CCR_RFLUSH(v) (((v) & 0x1) << 7) #define BFM_AIC_CCR_RFLUSH(v) BM_AIC_CCR_RFLUSH #define BF_AIC_CCR_RFLUSH_V(e) BF_AIC_CCR_RFLUSH(BV_AIC_CCR_RFLUSH__##e) #define BFM_AIC_CCR_RFLUSH_V(v) BM_AIC_CCR_RFLUSH #define BP_AIC_CCR_EROR 6 #define BM_AIC_CCR_EROR 0x40 #define BF_AIC_CCR_EROR(v) (((v) & 0x1) << 6) #define BFM_AIC_CCR_EROR(v) BM_AIC_CCR_EROR #define BF_AIC_CCR_EROR_V(e) BF_AIC_CCR_EROR(BV_AIC_CCR_EROR__##e) #define BFM_AIC_CCR_EROR_V(v) BM_AIC_CCR_EROR #define BP_AIC_CCR_ETUR 5 #define BM_AIC_CCR_ETUR 0x20 #define BF_AIC_CCR_ETUR(v) (((v) & 0x1) << 5) #define BFM_AIC_CCR_ETUR(v) BM_AIC_CCR_ETUR #define BF_AIC_CCR_ETUR_V(e) BF_AIC_CCR_ETUR(BV_AIC_CCR_ETUR__##e) #define BFM_AIC_CCR_ETUR_V(v) BM_AIC_CCR_ETUR #define BP_AIC_CCR_ERFS 4 #define BM_AIC_CCR_ERFS 0x10 #define BF_AIC_CCR_ERFS(v) (((v) & 0x1) << 4) #define BFM_AIC_CCR_ERFS(v) BM_AIC_CCR_ERFS #define BF_AIC_CCR_ERFS_V(e) BF_AIC_CCR_ERFS(BV_AIC_CCR_ERFS__##e) #define BFM_AIC_CCR_ERFS_V(v) BM_AIC_CCR_ERFS #define BP_AIC_CCR_ETFS 3 #define BM_AIC_CCR_ETFS 0x8 #define BF_AIC_CCR_ETFS(v) (((v) & 0x1) << 3) #define BFM_AIC_CCR_ETFS(v) BM_AIC_CCR_ETFS #define BF_AIC_CCR_ETFS_V(e) BF_AIC_CCR_ETFS(BV_AIC_CCR_ETFS__##e) #define BFM_AIC_CCR_ETFS_V(v) BM_AIC_CCR_ETFS #define BP_AIC_CCR_ENLBF 2 #define BM_AIC_CCR_ENLBF 0x4 #define BF_AIC_CCR_ENLBF(v) (((v) & 0x1) << 2) #define BFM_AIC_CCR_ENLBF(v) BM_AIC_CCR_ENLBF #define BF_AIC_CCR_ENLBF_V(e) BF_AIC_CCR_ENLBF(BV_AIC_CCR_ENLBF__##e) #define BFM_AIC_CCR_ENLBF_V(v) BM_AIC_CCR_ENLBF #define BP_AIC_CCR_ERPL 1 #define BM_AIC_CCR_ERPL 0x2 #define BF_AIC_CCR_ERPL(v) (((v) & 0x1) << 1) #define BFM_AIC_CCR_ERPL(v) BM_AIC_CCR_ERPL #define BF_AIC_CCR_ERPL_V(e) BF_AIC_CCR_ERPL(BV_AIC_CCR_ERPL__##e) #define BFM_AIC_CCR_ERPL_V(v) BM_AIC_CCR_ERPL #define BP_AIC_CCR_EREC 0 #define BM_AIC_CCR_EREC 0x1 #define BF_AIC_CCR_EREC(v) (((v) & 0x1) << 0) #define BFM_AIC_CCR_EREC(v) BM_AIC_CCR_EREC #define BF_AIC_CCR_EREC_V(e) BF_AIC_CCR_EREC(BV_AIC_CCR_EREC__##e) #define BFM_AIC_CCR_EREC_V(v) BM_AIC_CCR_EREC #define REG_AIC_I2SCR jz_reg(AIC_I2SCR) #define JA_AIC_I2SCR (0xb0020000 + 0x10) #define JT_AIC_I2SCR JIO_32_RW #define JN_AIC_I2SCR AIC_I2SCR #define JI_AIC_I2SCR #define BP_AIC_I2SCR_RFIRST 17 #define BM_AIC_I2SCR_RFIRST 0x20000 #define BF_AIC_I2SCR_RFIRST(v) (((v) & 0x1) << 17) #define BFM_AIC_I2SCR_RFIRST(v) BM_AIC_I2SCR_RFIRST #define BF_AIC_I2SCR_RFIRST_V(e) BF_AIC_I2SCR_RFIRST(BV_AIC_I2SCR_RFIRST__##e) #define BFM_AIC_I2SCR_RFIRST_V(v) BM_AIC_I2SCR_RFIRST #define BP_AIC_I2SCR_SWLH 16 #define BM_AIC_I2SCR_SWLH 0x10000 #define BF_AIC_I2SCR_SWLH(v) (((v) & 0x1) << 16) #define BFM_AIC_I2SCR_SWLH(v) BM_AIC_I2SCR_SWLH #define BF_AIC_I2SCR_SWLH_V(e) BF_AIC_I2SCR_SWLH(BV_AIC_I2SCR_SWLH__##e) #define BFM_AIC_I2SCR_SWLH_V(v) BM_AIC_I2SCR_SWLH #define BP_AIC_I2SCR_ISTPBK 13 #define BM_AIC_I2SCR_ISTPBK 0x2000 #define BF_AIC_I2SCR_ISTPBK(v) (((v) & 0x1) << 13) #define BFM_AIC_I2SCR_ISTPBK(v) BM_AIC_I2SCR_ISTPBK #define BF_AIC_I2SCR_ISTPBK_V(e) BF_AIC_I2SCR_ISTPBK(BV_AIC_I2SCR_ISTPBK__##e) #define BFM_AIC_I2SCR_ISTPBK_V(v) BM_AIC_I2SCR_ISTPBK #define BP_AIC_I2SCR_STPBK 12 #define BM_AIC_I2SCR_STPBK 0x1000 #define BF_AIC_I2SCR_STPBK(v) (((v) & 0x1) << 12) #define BFM_AIC_I2SCR_STPBK(v) BM_AIC_I2SCR_STPBK #define BF_AIC_I2SCR_STPBK_V(e) BF_AIC_I2SCR_STPBK(BV_AIC_I2SCR_STPBK__##e) #define BFM_AIC_I2SCR_STPBK_V(v) BM_AIC_I2SCR_STPBK #define BP_AIC_I2SCR_ESCLK 4 #define BM_AIC_I2SCR_ESCLK 0x10 #define BF_AIC_I2SCR_ESCLK(v) (((v) & 0x1) << 4) #define BFM_AIC_I2SCR_ESCLK(v) BM_AIC_I2SCR_ESCLK #define BF_AIC_I2SCR_ESCLK_V(e) BF_AIC_I2SCR_ESCLK(BV_AIC_I2SCR_ESCLK__##e) #define BFM_AIC_I2SCR_ESCLK_V(v) BM_AIC_I2SCR_ESCLK #define BP_AIC_I2SCR_AMSL 0 #define BM_AIC_I2SCR_AMSL 0x1 #define BF_AIC_I2SCR_AMSL(v) (((v) & 0x1) << 0) #define BFM_AIC_I2SCR_AMSL(v) BM_AIC_I2SCR_AMSL #define BF_AIC_I2SCR_AMSL_V(e) BF_AIC_I2SCR_AMSL(BV_AIC_I2SCR_AMSL__##e) #define BFM_AIC_I2SCR_AMSL_V(v) BM_AIC_I2SCR_AMSL #define REG_AIC_SR jz_reg(AIC_SR) #define JA_AIC_SR (0xb0020000 + 0x14) #define JT_AIC_SR JIO_32_RW #define JN_AIC_SR AIC_SR #define JI_AIC_SR #define BP_AIC_SR_RFL 24 #define BM_AIC_SR_RFL 0x3f000000 #define BF_AIC_SR_RFL(v) (((v) & 0x3f) << 24) #define BFM_AIC_SR_RFL(v) BM_AIC_SR_RFL #define BF_AIC_SR_RFL_V(e) BF_AIC_SR_RFL(BV_AIC_SR_RFL__##e) #define BFM_AIC_SR_RFL_V(v) BM_AIC_SR_RFL #define BP_AIC_SR_TFL 8 #define BM_AIC_SR_TFL 0x3f00 #define BF_AIC_SR_TFL(v) (((v) & 0x3f) << 8) #define BFM_AIC_SR_TFL(v) BM_AIC_SR_TFL #define BF_AIC_SR_TFL_V(e) BF_AIC_SR_TFL(BV_AIC_SR_TFL__##e) #define BFM_AIC_SR_TFL_V(v) BM_AIC_SR_TFL #define BP_AIC_SR_ROR 6 #define BM_AIC_SR_ROR 0x40 #define BF_AIC_SR_ROR(v) (((v) & 0x1) << 6) #define BFM_AIC_SR_ROR(v) BM_AIC_SR_ROR #define BF_AIC_SR_ROR_V(e) BF_AIC_SR_ROR(BV_AIC_SR_ROR__##e) #define BFM_AIC_SR_ROR_V(v) BM_AIC_SR_ROR #define BP_AIC_SR_TUR 5 #define BM_AIC_SR_TUR 0x20 #define BF_AIC_SR_TUR(v) (((v) & 0x1) << 5) #define BFM_AIC_SR_TUR(v) BM_AIC_SR_TUR #define BF_AIC_SR_TUR_V(e) BF_AIC_SR_TUR(BV_AIC_SR_TUR__##e) #define BFM_AIC_SR_TUR_V(v) BM_AIC_SR_TUR #define BP_AIC_SR_RFS 4 #define BM_AIC_SR_RFS 0x10 #define BF_AIC_SR_RFS(v) (((v) & 0x1) << 4) #define BFM_AIC_SR_RFS(v) BM_AIC_SR_RFS #define BF_AIC_SR_RFS_V(e) BF_AIC_SR_RFS(BV_AIC_SR_RFS__##e) #define BFM_AIC_SR_RFS_V(v) BM_AIC_SR_RFS #define BP_AIC_SR_TFS 3 #define BM_AIC_SR_TFS 0x8 #define BF_AIC_SR_TFS(v) (((v) & 0x1) << 3) #define BFM_AIC_SR_TFS(v) BM_AIC_SR_TFS #define BF_AIC_SR_TFS_V(e) BF_AIC_SR_TFS(BV_AIC_SR_TFS__##e) #define BFM_AIC_SR_TFS_V(v) BM_AIC_SR_TFS #define REG_AIC_I2SSR jz_reg(AIC_I2SSR) #define JA_AIC_I2SSR (0xb0020000 + 0x1c) #define JT_AIC_I2SSR JIO_32_RW #define JN_AIC_I2SSR AIC_I2SSR #define JI_AIC_I2SSR #define BP_AIC_I2SSR_CHBSY 5 #define BM_AIC_I2SSR_CHBSY 0x20 #define BF_AIC_I2SSR_CHBSY(v) (((v) & 0x1) << 5) #define BFM_AIC_I2SSR_CHBSY(v) BM_AIC_I2SSR_CHBSY #define BF_AIC_I2SSR_CHBSY_V(e) BF_AIC_I2SSR_CHBSY(BV_AIC_I2SSR_CHBSY__##e) #define BFM_AIC_I2SSR_CHBSY_V(v) BM_AIC_I2SSR_CHBSY #define BP_AIC_I2SSR_TBSY 4 #define BM_AIC_I2SSR_TBSY 0x10 #define BF_AIC_I2SSR_TBSY(v) (((v) & 0x1) << 4) #define BFM_AIC_I2SSR_TBSY(v) BM_AIC_I2SSR_TBSY #define BF_AIC_I2SSR_TBSY_V(e) BF_AIC_I2SSR_TBSY(BV_AIC_I2SSR_TBSY__##e) #define BFM_AIC_I2SSR_TBSY_V(v) BM_AIC_I2SSR_TBSY #define BP_AIC_I2SSR_RBSY 3 #define BM_AIC_I2SSR_RBSY 0x8 #define BF_AIC_I2SSR_RBSY(v) (((v) & 0x1) << 3) #define BFM_AIC_I2SSR_RBSY(v) BM_AIC_I2SSR_RBSY #define BF_AIC_I2SSR_RBSY_V(e) BF_AIC_I2SSR_RBSY(BV_AIC_I2SSR_RBSY__##e) #define BFM_AIC_I2SSR_RBSY_V(v) BM_AIC_I2SSR_RBSY #define BP_AIC_I2SSR_BSY 2 #define BM_AIC_I2SSR_BSY 0x4 #define BF_AIC_I2SSR_BSY(v) (((v) & 0x1) << 2) #define BFM_AIC_I2SSR_BSY(v) BM_AIC_I2SSR_BSY #define BF_AIC_I2SSR_BSY_V(e) BF_AIC_I2SSR_BSY(BV_AIC_I2SSR_BSY__##e) #define BFM_AIC_I2SSR_BSY_V(v) BM_AIC_I2SSR_BSY #define REG_AIC_I2SDIV jz_reg(AIC_I2SDIV) #define JA_AIC_I2SDIV (0xb0020000 + 0x30) #define JT_AIC_I2SDIV JIO_32_RW #define JN_AIC_I2SDIV AIC_I2SDIV #define JI_AIC_I2SDIV #define REG_AIC_DR jz_reg(AIC_DR) #define JA_AIC_DR (0xb0020000 + 0x34) #define JT_AIC_DR JIO_32_RW #define JN_AIC_DR AIC_DR #define JI_AIC_DR #define REG_AIC_SPENA jz_reg(AIC_SPENA) #define JA_AIC_SPENA (0xb0020000 + 0x80) #define JT_AIC_SPENA JIO_32_RW #define JN_AIC_SPENA AIC_SPENA #define JI_AIC_SPENA #define REG_AIC_SPCTRL jz_reg(AIC_SPCTRL) #define JA_AIC_SPCTRL (0xb0020000 + 0x84) #define JT_AIC_SPCTRL JIO_32_RW #define JN_AIC_SPCTRL AIC_SPCTRL #define JI_AIC_SPCTRL #define BP_AIC_SPCTRL_DMA_EN 15 #define BM_AIC_SPCTRL_DMA_EN 0x8000 #define BF_AIC_SPCTRL_DMA_EN(v) (((v) & 0x1) << 15) #define BFM_AIC_SPCTRL_DMA_EN(v) BM_AIC_SPCTRL_DMA_EN #define BF_AIC_SPCTRL_DMA_EN_V(e) BF_AIC_SPCTRL_DMA_EN(BV_AIC_SPCTRL_DMA_EN__##e) #define BFM_AIC_SPCTRL_DMA_EN_V(v) BM_AIC_SPCTRL_DMA_EN #define BP_AIC_SPCTRL_D_TYPE 14 #define BM_AIC_SPCTRL_D_TYPE 0x4000 #define BF_AIC_SPCTRL_D_TYPE(v) (((v) & 0x1) << 14) #define BFM_AIC_SPCTRL_D_TYPE(v) BM_AIC_SPCTRL_D_TYPE #define BF_AIC_SPCTRL_D_TYPE_V(e) BF_AIC_SPCTRL_D_TYPE(BV_AIC_SPCTRL_D_TYPE__##e) #define BFM_AIC_SPCTRL_D_TYPE_V(v) BM_AIC_SPCTRL_D_TYPE #define BP_AIC_SPCTRL_SIGN_N 13 #define BM_AIC_SPCTRL_SIGN_N 0x2000 #define BF_AIC_SPCTRL_SIGN_N(v) (((v) & 0x1) << 13) #define BFM_AIC_SPCTRL_SIGN_N(v) BM_AIC_SPCTRL_SIGN_N #define BF_AIC_SPCTRL_SIGN_N_V(e) BF_AIC_SPCTRL_SIGN_N(BV_AIC_SPCTRL_SIGN_N__##e) #define BFM_AIC_SPCTRL_SIGN_N_V(v) BM_AIC_SPCTRL_SIGN_N #define BP_AIC_SPCTRL_INVALID 12 #define BM_AIC_SPCTRL_INVALID 0x1000 #define BF_AIC_SPCTRL_INVALID(v) (((v) & 0x1) << 12) #define BFM_AIC_SPCTRL_INVALID(v) BM_AIC_SPCTRL_INVALID #define BF_AIC_SPCTRL_INVALID_V(e) BF_AIC_SPCTRL_INVALID(BV_AIC_SPCTRL_INVALID__##e) #define BFM_AIC_SPCTRL_INVALID_V(v) BM_AIC_SPCTRL_INVALID #define BP_AIC_SPCTRL_SFT_RST 11 #define BM_AIC_SPCTRL_SFT_RST 0x800 #define BF_AIC_SPCTRL_SFT_RST(v) (((v) & 0x1) << 11) #define BFM_AIC_SPCTRL_SFT_RST(v) BM_AIC_SPCTRL_SFT_RST #define BF_AIC_SPCTRL_SFT_RST_V(e) BF_AIC_SPCTRL_SFT_RST(BV_AIC_SPCTRL_SFT_RST__##e) #define BFM_AIC_SPCTRL_SFT_RST_V(v) BM_AIC_SPCTRL_SFT_RST #define BP_AIC_SPCTRL_SPDIF_I2S 10 #define BM_AIC_SPCTRL_SPDIF_I2S 0x400 #define BF_AIC_SPCTRL_SPDIF_I2S(v) (((v) & 0x1) << 10) #define BFM_AIC_SPCTRL_SPDIF_I2S(v) BM_AIC_SPCTRL_SPDIF_I2S #define BF_AIC_SPCTRL_SPDIF_I2S_V(e) BF_AIC_SPCTRL_SPDIF_I2S(BV_AIC_SPCTRL_SPDIF_I2S__##e) #define BFM_AIC_SPCTRL_SPDIF_I2S_V(v) BM_AIC_SPCTRL_SPDIF_I2S #define BP_AIC_SPCTRL_M_TRIG 1 #define BM_AIC_SPCTRL_M_TRIG 0x2 #define BF_AIC_SPCTRL_M_TRIG(v) (((v) & 0x1) << 1) #define BFM_AIC_SPCTRL_M_TRIG(v) BM_AIC_SPCTRL_M_TRIG #define BF_AIC_SPCTRL_M_TRIG_V(e) BF_AIC_SPCTRL_M_TRIG(BV_AIC_SPCTRL_M_TRIG__##e) #define BFM_AIC_SPCTRL_M_TRIG_V(v) BM_AIC_SPCTRL_M_TRIG #define BP_AIC_SPCTRL_M_FFUR 0 #define BM_AIC_SPCTRL_M_FFUR 0x1 #define BF_AIC_SPCTRL_M_FFUR(v) (((v) & 0x1) << 0) #define BFM_AIC_SPCTRL_M_FFUR(v) BM_AIC_SPCTRL_M_FFUR #define BF_AIC_SPCTRL_M_FFUR_V(e) BF_AIC_SPCTRL_M_FFUR(BV_AIC_SPCTRL_M_FFUR__##e) #define BFM_AIC_SPCTRL_M_FFUR_V(v) BM_AIC_SPCTRL_M_FFUR #define REG_AIC_SPSTATE jz_reg(AIC_SPSTATE) #define JA_AIC_SPSTATE (0xb0020000 + 0x88) #define JT_AIC_SPSTATE JIO_32_RW #define JN_AIC_SPSTATE AIC_SPSTATE #define JI_AIC_SPSTATE #define BP_AIC_SPSTATE_FIFO_LEVEL 8 #define BM_AIC_SPSTATE_FIFO_LEVEL 0x7f00 #define BF_AIC_SPSTATE_FIFO_LEVEL(v) (((v) & 0x7f) << 8) #define BFM_AIC_SPSTATE_FIFO_LEVEL(v) BM_AIC_SPSTATE_FIFO_LEVEL #define BF_AIC_SPSTATE_FIFO_LEVEL_V(e) BF_AIC_SPSTATE_FIFO_LEVEL(BV_AIC_SPSTATE_FIFO_LEVEL__##e) #define BFM_AIC_SPSTATE_FIFO_LEVEL_V(v) BM_AIC_SPSTATE_FIFO_LEVEL #define BP_AIC_SPSTATE_BUSY 7 #define BM_AIC_SPSTATE_BUSY 0x80 #define BF_AIC_SPSTATE_BUSY(v) (((v) & 0x1) << 7) #define BFM_AIC_SPSTATE_BUSY(v) BM_AIC_SPSTATE_BUSY #define BF_AIC_SPSTATE_BUSY_V(e) BF_AIC_SPSTATE_BUSY(BV_AIC_SPSTATE_BUSY__##e) #define BFM_AIC_SPSTATE_BUSY_V(v) BM_AIC_SPSTATE_BUSY #define BP_AIC_SPSTATE_F_TRIG 1 #define BM_AIC_SPSTATE_F_TRIG 0x2 #define BF_AIC_SPSTATE_F_TRIG(v) (((v) & 0x1) << 1) #define BFM_AIC_SPSTATE_F_TRIG(v) BM_AIC_SPSTATE_F_TRIG #define BF_AIC_SPSTATE_F_TRIG_V(e) BF_AIC_SPSTATE_F_TRIG(BV_AIC_SPSTATE_F_TRIG__##e) #define BFM_AIC_SPSTATE_F_TRIG_V(v) BM_AIC_SPSTATE_F_TRIG #define BP_AIC_SPSTATE_F_FFUR 0 #define BM_AIC_SPSTATE_F_FFUR 0x1 #define BF_AIC_SPSTATE_F_FFUR(v) (((v) & 0x1) << 0) #define BFM_AIC_SPSTATE_F_FFUR(v) BM_AIC_SPSTATE_F_FFUR #define BF_AIC_SPSTATE_F_FFUR_V(e) BF_AIC_SPSTATE_F_FFUR(BV_AIC_SPSTATE_F_FFUR__##e) #define BFM_AIC_SPSTATE_F_FFUR_V(v) BM_AIC_SPSTATE_F_FFUR #define REG_AIC_SPCFG1 jz_reg(AIC_SPCFG1) #define JA_AIC_SPCFG1 (0xb0020000 + 0x8c) #define JT_AIC_SPCFG1 JIO_32_RW #define JN_AIC_SPCFG1 AIC_SPCFG1 #define JI_AIC_SPCFG1 #define BP_AIC_SPCFG1_TRIG 12 #define BM_AIC_SPCFG1_TRIG 0x3000 #define BF_AIC_SPCFG1_TRIG(v) (((v) & 0x3) << 12) #define BFM_AIC_SPCFG1_TRIG(v) BM_AIC_SPCFG1_TRIG #define BF_AIC_SPCFG1_TRIG_V(e) BF_AIC_SPCFG1_TRIG(BV_AIC_SPCFG1_TRIG__##e) #define BFM_AIC_SPCFG1_TRIG_V(v) BM_AIC_SPCFG1_TRIG #define BP_AIC_SPCFG1_SRC_NUM 8 #define BM_AIC_SPCFG1_SRC_NUM 0xf00 #define BF_AIC_SPCFG1_SRC_NUM(v) (((v) & 0xf) << 8) #define BFM_AIC_SPCFG1_SRC_NUM(v) BM_AIC_SPCFG1_SRC_NUM #define BF_AIC_SPCFG1_SRC_NUM_V(e) BF_AIC_SPCFG1_SRC_NUM(BV_AIC_SPCFG1_SRC_NUM__##e) #define BFM_AIC_SPCFG1_SRC_NUM_V(v) BM_AIC_SPCFG1_SRC_NUM #define BP_AIC_SPCFG1_CH1_NUM 4 #define BM_AIC_SPCFG1_CH1_NUM 0xf0 #define BF_AIC_SPCFG1_CH1_NUM(v) (((v) & 0xf) << 4) #define BFM_AIC_SPCFG1_CH1_NUM(v) BM_AIC_SPCFG1_CH1_NUM #define BF_AIC_SPCFG1_CH1_NUM_V(e) BF_AIC_SPCFG1_CH1_NUM(BV_AIC_SPCFG1_CH1_NUM__##e) #define BFM_AIC_SPCFG1_CH1_NUM_V(v) BM_AIC_SPCFG1_CH1_NUM #define BP_AIC_SPCFG1_CH2_NUM 0 #define BM_AIC_SPCFG1_CH2_NUM 0xf #define BF_AIC_SPCFG1_CH2_NUM(v) (((v) & 0xf) << 0) #define BFM_AIC_SPCFG1_CH2_NUM(v) BM_AIC_SPCFG1_CH2_NUM #define BF_AIC_SPCFG1_CH2_NUM_V(e) BF_AIC_SPCFG1_CH2_NUM(BV_AIC_SPCFG1_CH2_NUM__##e) #define BFM_AIC_SPCFG1_CH2_NUM_V(v) BM_AIC_SPCFG1_CH2_NUM #define BP_AIC_SPCFG1_INIT_LEVEL 17 #define BM_AIC_SPCFG1_INIT_LEVEL 0x20000 #define BF_AIC_SPCFG1_INIT_LEVEL(v) (((v) & 0x1) << 17) #define BFM_AIC_SPCFG1_INIT_LEVEL(v) BM_AIC_SPCFG1_INIT_LEVEL #define BF_AIC_SPCFG1_INIT_LEVEL_V(e) BF_AIC_SPCFG1_INIT_LEVEL(BV_AIC_SPCFG1_INIT_LEVEL__##e) #define BFM_AIC_SPCFG1_INIT_LEVEL_V(v) BM_AIC_SPCFG1_INIT_LEVEL #define BP_AIC_SPCFG1_ZERO_VALID 16 #define BM_AIC_SPCFG1_ZERO_VALID 0x10000 #define BF_AIC_SPCFG1_ZERO_VALID(v) (((v) & 0x1) << 16) #define BFM_AIC_SPCFG1_ZERO_VALID(v) BM_AIC_SPCFG1_ZERO_VALID #define BF_AIC_SPCFG1_ZERO_VALID_V(e) BF_AIC_SPCFG1_ZERO_VALID(BV_AIC_SPCFG1_ZERO_VALID__##e) #define BFM_AIC_SPCFG1_ZERO_VALID_V(v) BM_AIC_SPCFG1_ZERO_VALID #define REG_AIC_SPCFG2 jz_reg(AIC_SPCFG2) #define JA_AIC_SPCFG2 (0xb0020000 + 0x90) #define JT_AIC_SPCFG2 JIO_32_RW #define JN_AIC_SPCFG2 AIC_SPCFG2 #define JI_AIC_SPCFG2 #define BP_AIC_SPCFG2_FS 26 #define BM_AIC_SPCFG2_FS 0x3c000000 #define BF_AIC_SPCFG2_FS(v) (((v) & 0xf) << 26) #define BFM_AIC_SPCFG2_FS(v) BM_AIC_SPCFG2_FS #define BF_AIC_SPCFG2_FS_V(e) BF_AIC_SPCFG2_FS(BV_AIC_SPCFG2_FS__##e) #define BFM_AIC_SPCFG2_FS_V(v) BM_AIC_SPCFG2_FS #define BP_AIC_SPCFG2_ORG_FRQ 22 #define BM_AIC_SPCFG2_ORG_FRQ 0x3c00000 #define BF_AIC_SPCFG2_ORG_FRQ(v) (((v) & 0xf) << 22) #define BFM_AIC_SPCFG2_ORG_FRQ(v) BM_AIC_SPCFG2_ORG_FRQ #define BF_AIC_SPCFG2_ORG_FRQ_V(e) BF_AIC_SPCFG2_ORG_FRQ(BV_AIC_SPCFG2_ORG_FRQ__##e) #define BFM_AIC_SPCFG2_ORG_FRQ_V(v) BM_AIC_SPCFG2_ORG_FRQ #define BP_AIC_SPCFG2_SAMPL_WL 19 #define BM_AIC_SPCFG2_SAMPL_WL 0x380000 #define BF_AIC_SPCFG2_SAMPL_WL(v) (((v) & 0x7) << 19) #define BFM_AIC_SPCFG2_SAMPL_WL(v) BM_AIC_SPCFG2_SAMPL_WL #define BF_AIC_SPCFG2_SAMPL_WL_V(e) BF_AIC_SPCFG2_SAMPL_WL(BV_AIC_SPCFG2_SAMPL_WL__##e) #define BFM_AIC_SPCFG2_SAMPL_WL_V(v) BM_AIC_SPCFG2_SAMPL_WL #define BP_AIC_SPCFG2_CLK_ACU 16 #define BM_AIC_SPCFG2_CLK_ACU 0x30000 #define BF_AIC_SPCFG2_CLK_ACU(v) (((v) & 0x3) << 16) #define BFM_AIC_SPCFG2_CLK_ACU(v) BM_AIC_SPCFG2_CLK_ACU #define BF_AIC_SPCFG2_CLK_ACU_V(e) BF_AIC_SPCFG2_CLK_ACU(BV_AIC_SPCFG2_CLK_ACU__##e) #define BFM_AIC_SPCFG2_CLK_ACU_V(v) BM_AIC_SPCFG2_CLK_ACU #define BP_AIC_SPCFG2_CAT_CODE 8 #define BM_AIC_SPCFG2_CAT_CODE 0xff00 #define BF_AIC_SPCFG2_CAT_CODE(v) (((v) & 0xff) << 8) #define BFM_AIC_SPCFG2_CAT_CODE(v) BM_AIC_SPCFG2_CAT_CODE #define BF_AIC_SPCFG2_CAT_CODE_V(e) BF_AIC_SPCFG2_CAT_CODE(BV_AIC_SPCFG2_CAT_CODE__##e) #define BFM_AIC_SPCFG2_CAT_CODE_V(v) BM_AIC_SPCFG2_CAT_CODE #define BP_AIC_SPCFG2_CH_MD 6 #define BM_AIC_SPCFG2_CH_MD 0xc0 #define BF_AIC_SPCFG2_CH_MD(v) (((v) & 0x3) << 6) #define BFM_AIC_SPCFG2_CH_MD(v) BM_AIC_SPCFG2_CH_MD #define BF_AIC_SPCFG2_CH_MD_V(e) BF_AIC_SPCFG2_CH_MD(BV_AIC_SPCFG2_CH_MD__##e) #define BFM_AIC_SPCFG2_CH_MD_V(v) BM_AIC_SPCFG2_CH_MD #define BP_AIC_SPCFG2_MAX_WL 18 #define BM_AIC_SPCFG2_MAX_WL 0x40000 #define BF_AIC_SPCFG2_MAX_WL(v) (((v) & 0x1) << 18) #define BFM_AIC_SPCFG2_MAX_WL(v) BM_AIC_SPCFG2_MAX_WL #define BF_AIC_SPCFG2_MAX_WL_V(e) BF_AIC_SPCFG2_MAX_WL(BV_AIC_SPCFG2_MAX_WL__##e) #define BFM_AIC_SPCFG2_MAX_WL_V(v) BM_AIC_SPCFG2_MAX_WL #define BP_AIC_SPCFG2_PRE 3 #define BM_AIC_SPCFG2_PRE 0x8 #define BF_AIC_SPCFG2_PRE(v) (((v) & 0x1) << 3) #define BFM_AIC_SPCFG2_PRE(v) BM_AIC_SPCFG2_PRE #define BF_AIC_SPCFG2_PRE_V(e) BF_AIC_SPCFG2_PRE(BV_AIC_SPCFG2_PRE__##e) #define BFM_AIC_SPCFG2_PRE_V(v) BM_AIC_SPCFG2_PRE #define BP_AIC_SPCFG2_COPY_N 2 #define BM_AIC_SPCFG2_COPY_N 0x4 #define BF_AIC_SPCFG2_COPY_N(v) (((v) & 0x1) << 2) #define BFM_AIC_SPCFG2_COPY_N(v) BM_AIC_SPCFG2_COPY_N #define BF_AIC_SPCFG2_COPY_N_V(e) BF_AIC_SPCFG2_COPY_N(BV_AIC_SPCFG2_COPY_N__##e) #define BFM_AIC_SPCFG2_COPY_N_V(v) BM_AIC_SPCFG2_COPY_N #define BP_AIC_SPCFG2_AUDIO_N 1 #define BM_AIC_SPCFG2_AUDIO_N 0x2 #define BF_AIC_SPCFG2_AUDIO_N(v) (((v) & 0x1) << 1) #define BFM_AIC_SPCFG2_AUDIO_N(v) BM_AIC_SPCFG2_AUDIO_N #define BF_AIC_SPCFG2_AUDIO_N_V(e) BF_AIC_SPCFG2_AUDIO_N(BV_AIC_SPCFG2_AUDIO_N__##e) #define BFM_AIC_SPCFG2_AUDIO_N_V(v) BM_AIC_SPCFG2_AUDIO_N #define BP_AIC_SPCFG2_CON_PRO 0 #define BM_AIC_SPCFG2_CON_PRO 0x1 #define BF_AIC_SPCFG2_CON_PRO(v) (((v) & 0x1) << 0) #define BFM_AIC_SPCFG2_CON_PRO(v) BM_AIC_SPCFG2_CON_PRO #define BF_AIC_SPCFG2_CON_PRO_V(e) BF_AIC_SPCFG2_CON_PRO(BV_AIC_SPCFG2_CON_PRO__##e) #define BFM_AIC_SPCFG2_CON_PRO_V(v) BM_AIC_SPCFG2_CON_PRO #define REG_AIC_SPFIFO jz_reg(AIC_SPFIFO) #define JA_AIC_SPFIFO (0xb0020000 + 0x94) #define JT_AIC_SPFIFO JIO_32_RW #define JN_AIC_SPFIFO AIC_SPFIFO #define JI_AIC_SPFIFO #define REG_AIC_RGADW jz_reg(AIC_RGADW) #define JA_AIC_RGADW (0xb0020000 + 0xa4) #define JT_AIC_RGADW JIO_32_RW #define JN_AIC_RGADW AIC_RGADW #define JI_AIC_RGADW #define BP_AIC_RGADW_ADDR 8 #define BM_AIC_RGADW_ADDR 0x7f00 #define BF_AIC_RGADW_ADDR(v) (((v) & 0x7f) << 8) #define BFM_AIC_RGADW_ADDR(v) BM_AIC_RGADW_ADDR #define BF_AIC_RGADW_ADDR_V(e) BF_AIC_RGADW_ADDR(BV_AIC_RGADW_ADDR__##e) #define BFM_AIC_RGADW_ADDR_V(v) BM_AIC_RGADW_ADDR #define BP_AIC_RGADW_DATA 0 #define BM_AIC_RGADW_DATA 0xff #define BF_AIC_RGADW_DATA(v) (((v) & 0xff) << 0) #define BFM_AIC_RGADW_DATA(v) BM_AIC_RGADW_DATA #define BF_AIC_RGADW_DATA_V(e) BF_AIC_RGADW_DATA(BV_AIC_RGADW_DATA__##e) #define BFM_AIC_RGADW_DATA_V(v) BM_AIC_RGADW_DATA #define BP_AIC_RGADW_ICRST 31 #define BM_AIC_RGADW_ICRST 0x80000000 #define BF_AIC_RGADW_ICRST(v) (((v) & 0x1) << 31) #define BFM_AIC_RGADW_ICRST(v) BM_AIC_RGADW_ICRST #define BF_AIC_RGADW_ICRST_V(e) BF_AIC_RGADW_ICRST(BV_AIC_RGADW_ICRST__##e) #define BFM_AIC_RGADW_ICRST_V(v) BM_AIC_RGADW_ICRST #define BP_AIC_RGADW_RGWR 16 #define BM_AIC_RGADW_RGWR 0x10000 #define BF_AIC_RGADW_RGWR(v) (((v) & 0x1) << 16) #define BFM_AIC_RGADW_RGWR(v) BM_AIC_RGADW_RGWR #define BF_AIC_RGADW_RGWR_V(e) BF_AIC_RGADW_RGWR(BV_AIC_RGADW_RGWR__##e) #define BFM_AIC_RGADW_RGWR_V(v) BM_AIC_RGADW_RGWR #define REG_AIC_RGDATA jz_reg(AIC_RGDATA) #define JA_AIC_RGDATA (0xb0020000 + 0xa8) #define JT_AIC_RGDATA JIO_32_RW #define JN_AIC_RGDATA AIC_RGDATA #define JI_AIC_RGDATA #define BP_AIC_RGDATA_DATA 0 #define BM_AIC_RGDATA_DATA 0xff #define BF_AIC_RGDATA_DATA(v) (((v) & 0xff) << 0) #define BFM_AIC_RGDATA_DATA(v) BM_AIC_RGDATA_DATA #define BF_AIC_RGDATA_DATA_V(e) BF_AIC_RGDATA_DATA(BV_AIC_RGDATA_DATA__##e) #define BFM_AIC_RGDATA_DATA_V(v) BM_AIC_RGDATA_DATA #define BP_AIC_RGDATA_IRQ 8 #define BM_AIC_RGDATA_IRQ 0x100 #define BF_AIC_RGDATA_IRQ(v) (((v) & 0x1) << 8) #define BFM_AIC_RGDATA_IRQ(v) BM_AIC_RGDATA_IRQ #define BF_AIC_RGDATA_IRQ_V(e) BF_AIC_RGDATA_IRQ(BV_AIC_RGDATA_IRQ__##e) #define BFM_AIC_RGDATA_IRQ_V(v) BM_AIC_RGDATA_IRQ #endif /* __HEADERGEN_AIC_H__*/