atj213x Marcin Bukat ADC ADC

0xb0110000

ATA ATA

0xb0090000

CONFIG CONFIG

0x0

UDMACTL UDMACTL

0x4

DATA DATA

0x8

FEATURE FEATURE

0xc

SECCNT SECCNT

0x10

SECNUM SECNUM

0x14

CLDLOW CLDL

0x18

CLDHI CLDHIGH

0x1c

HEAD HEAD

0x20

CMD CMD

0x24

BYTECNT BYTECNT

0x28

FIFOCTL FIFOCTL

0x2c

FIFOCFG FIFOCFG

0x30

ADDRDEC ADDRDEC

0x34

IRQCTL IRQCTL

0x38

BOOT BOOT

0xb0038000

NORCTL NORCTL

0x0

BROMCTL BROMCTL

0x4

CHIPID CHIPID

0x8

BT BT

0xb00d0000

CMU CMU

0xb0010000

COREPLL COREPLL

0x0

RESERVED31_11 11 21 CPBY Core PLL Bypass 10 CPBI Core PLL Bias 8 2 CPEN Core PLL Enable 7 HOEN High Oscillator Enable 6 CPCK COREPLLout = CPCK * 6 (MHz) (in range 12 - 378MHz) 0 6 DSPPLL DSPPLL

0x4

RESERVED31_9 9 23 DPBI DSP PLL Bias 7 2 DPEN DSP PLL Enable 6 DPCK DSPPLLout = DPCK * 6 (MHz) (in range 12-378MHz) 0 6 AUDIOPLL AUDIOPLL

0x8

RESERVED31_12 12 20 ADCPLL Audio PLL CLk Control 11 ADCCLK ADC Clock Divisor, output is FS*256 8 3 RESERVED7 7 APBI Audio PLL Bias 5 2 APEN Audio PLL Enable 4 DACPLL DAC PLL CLk Control 3 DACCLK DAC Clock Divisor, output is FS*256 0 3 BUSCLK BUSCLK

0xc

Bus CLK Control Register KEYE Key Wakeup Enable 31 ALME Alarm Wakeup Enable 30 SIRE SIRQ Wakeup Enable 29 RESERVED28 28 USBE Usb Wakeup Enable 27 RESERVED26_12 12 15 PCLKDIV Peripheral CLK Divisor 8 4 CORECLKS CPU Clock Selection 6 2 SCLKDIV System Clock Divisor 4 2 CCLKDIV CPU Clock Divisor 2 2 DCEN Core CLK DC Enable 1 SDRCLK SDRCLK

0x10

SDRAM Interface CLK Control Register RESERVED31_2 2 30 SDRDIV 0 2 NANDCLK NANDCLK

0x18

NAND Interface CLK Control Register RESERVED31_4 4 28 NANDDIV 0 4 SDCLK SDCLK

0x1c

SD Interface CLK Control Register RESERVED31_6 6 26 CKEN SD Interface Clock Enable 5 D128 Enable Divide 128 circuit 4 SDDIV 0 4 MHACLK MHACLK

0x20

MHA CLK Control Register RESERVED31_4 4 28 MHADIV 0 4 UART2CLK UART2CLK

0x2c

Uart2 CLK Control Register RESERVED31_17 17 15 U2EN Uart2 Clock Enable 16 UART2DIV 0 16 DMACLK DMACLK

0x30

DMA CLK Control Register RESERVED31_4 4 28 D7EN DMA 7 (Special Channel) Clock Enable 3 D6EN DMA 6 (Special Channel) Clock Enable 2 D5EN DMA 5 (Special Channel) Clock Enable 1 D4EN DMA 4 (Special Channel) Clock Enable 0 FMCLK FMCLK

0x34

FM CLK Control Register RESERVED31_6 6 26 BCKE PWM Back Light clock Enable 5 BCKS Back Light CLK source select 4 BCKCON Divided PWM Back Light Special Clock Control 2 2 CLKS FM Clock Output Selection 1 OUTE FM Clock Output Enable (From Test Pin) 0 MCACLK MCACLK

0x38

MCA CLK Control Register RESERVED31_4 4 28 MCADIV 0 4 DEVCLKEN DEVCLKEN

0x80

Device CLK Control Register RESERVED31_27 27 5 GPIO 26 KEY 25 RESERVED24 24 I2C 23 UART 22 RESERVED21_19 19 3 ADC 18 DAC 17 DSPC 16 MCA 15 MHA 14 USBC 13 RESERVED12 12 SD 11 RESERVED10 10 NAND 9 DMAC 8 PCNT 7 SDRM 6 SDRC 5 DSPM 4 RESERVED3 3 RMOC 2 YUV 1 RESERVED0 0 DEVRST DEVRST

0x84

Device Reset Control Register RESERVED31 31 GPIO 30 KEY 29 RESERVED28 28 I2C 27 UART 26 RESERVED25_23 23 3 ADC 22 DAC 21 DSPC DSP control block reset 20 INTC 19 RTC 18 PMU 17 RESERVED16_14 14 3 DSPM SRAM DSP MEM reset 13 TVENC 12 YUV 11 MCA 10 USB 9 RESERVED8 8 MHA 7 SD 6 NAND 5 RESERVED4 4 DMAC 3 PCNT 2 RESERVED1 1 SDR SDRAM Control register and SDRAM block Reset 0 DAC DAC

0xb0100000

DMAC Channels 0-3 work with retular AHB bus, channels 4-7 work with 'special' bus. DMAC

0xb0060000

CTL CTL

0x0

IRQEN IRQEN

0x4

IRQPD IRQPD

0x8

DMA_MODE DMA_MODE 0 8 0x100 0x20 DBURLEN Destination burst length. If burst lenght is 4 or 8 DDIR must be 0, DFXA must be 0, DDSP must be 0, DCOL must be 0. Burst must not cross a 1kB address boundary. 29 3 SINGLE 0x0 INCR4 0x3 INCR8 0x5 RELO DMA Reload Bit. 28 DDSP Destination DSP mode. 27 DCOL Destination Column Mode. 26 DDIR Destination address direction. If DBURLEN is INCR4 or INCR8 only INCREASE is allowed. 25 INCREASE 0x0 DECREASE 0x1 DFXA Destination Fixed Address bit. 24 NOT_FIXED 0x0 FIXED 0x1 DTRG Destination DRQ Trig Source. 19 5 DAC 0x6 SDRAM 0x10 IRAM 0x11 SD 0x16 OTG 0x17 LCM 0x18 DTRANWID 17 2 WIDTH8 0x0 WIDTH16 0x1 WIDTH32 0x2 DFXS If DFXS=0, DMA will transfer in 8bit mode when remain counter is less than DTRANWID. If DFXS=1, DMA will always transfer in DTRANWID. 16 SBURLEN Source burst length. If burst lenght is 4 or 8 DDIR must be 0, DFXA must be 0, DDSP must be 0, DCOL must be 0. Burst must not cross a 1kB address boundary. 13 3 SINGLE 0x0 INCR4 0x3 INCR8 0x5 SDSP Source DSP mode. 11 SCOL Source Column Mode. 10 SDIR Source address direction. If SBURLEN is INCR4 or INCR8 only INCREASE is allowed. 9 INCREASE 0x0 DECREASE 0x1 SFXA Source Fixed Addres bit. 8 NOT_FIXED 0x0 FIXED 0x1 STRG DRQ trig source. 3 5 DAC 0x6 SDRAM 0x10 IRAM 0x11 SD 0x16 OTG 0x17 LCM 0x18 STRANWID 1 2 WIDTH8 0x0 WIDTH16 0x1 WIDTH32 0x2 SFXS Source Fix Size. If DFXS=0, DMA will transfer in 8bit mode when remain counter is less than STRANWID. If SFXS=1, DMA will always transfer in STRANWID. 0 DMA_SRC DMA_SRC 0 8 0x104 0x20 DMA_DST DMA_DST 0 8 0x108 0x20 DMA_CNT DMA_CNT 0 8 0x10c 0x20 DMA_REM DMA_REM 0 8 0x110 0x20 DMA_CMD DMA_CMD 0 8 0x114 0x20 DSP DSP

0xb0050000

HDR HDR0

0x0

HDR1

0x4

HDR2

0x8

HDR3

0xc

HDR4

0x10

HDR5

0x14

HSR6

0x18

HSR7

0x1c

HIP data registers CTL CTL

0x20

GPIO GPIO

0xb01c0000

OUTEN AOUTEN

0x0

BOUTEN

0xc

INEN AINEN

0x4

BINEN

0x10

DAT ADAT

0x8

BDAT

0x14

MFCTL0 MFCTL0

0x18

RESERVED31_25 25 7 GPIOA2_0 22 3 NAND_CLE_RB_ALE 0x1 LCD_RS_WD9_WD0 0x2 SD_CMD 0x4 CEB6 20 2 LCD_CE 0x2 SD_CLK 0x3 RESERVED19_16 16 4 CEB3 14 2 NAND_CEB3 0x1 LCD_CE 0x2 CEB2 12 2 NAND_CEB2 0x1 LCD_CE 0x2 CEB1 10 2 NAND_CEB1 0x1 LCD_CE 0x2 CEB0 8 2 NAND_CEB0 0x1 LCD_CE 0x2 WRRD 6 2 NAND_WR_RD 0x1 LCD_WRB_RDB 0x2 NAND_D7_0 3 3 NAND_D7_0 0x1 LCD_WD17_10 0x2 NAND_D15_8 0 3 NAND_D15_8 0x1 LCD_WD8_1 0x2 SDR_D7_0 0x4 MFCTL1 MFCTL1

0x1c

MFEN 31 RESERVED30_18 18 13 SD2E 17 RBS 16 RESERVED15_12 12 4 SIR0 11 SPTR 9 2 I2C1_SCL_ADA 0x1 UART2_TX_RX 0x2 U2TR 8 UART2_TX_RX 0x0 I2C2_SCL_SDA 0x1 RESERVED7_6 6 2 I2C1SS 4 2 I2C1_SCL_SDA 0x0 UART2_TX_RX 0x1 RESERVED3_0 0 4 I2C I2C 1

0xb0180000

0xb0180020

CTL CTL

0x0

RESERVED31_9 9 23 PUEN nternal Pull-up Resistor (4.7k) Enable 8 EN Block enable 7 SIE START Condition Generates IRQ Enable (only for slave mode) 6 IRQE IRQ Enable 5 MS Mode select 4 MASTER 0x0 SLAVE 0x1 GBCC Generating Bus Control Condition (only for master mode) 2 2 NOP 0x0 START 0x1 STOP 0x2 REPEATED_START 0x3 RB Release Bus. Writing 1 to this bit will release the clock and data line to idle. MCU should write 1 to this bit after transmitting or receiving the last bit of the whole transfer. 1 GRAS Generating/Receiving Acknowledge Signal 0 CLKDIV CLKDIV

0x4

RESERVED31_8 8 24 CLKDIV Clock Divider Factor (only for master mode). I2Cx clock (SCL) can select standard (100kbps) mode and fast (400kbps) mode. Calculating SCL is as follows: SCL=PCLK/(CLKDIV*16) 0 8 STAT STAT

0x8

RESERVED31_8 8 24 TRC Transmit/Receive Complete Bit 7 STPD STOP Detect Bit 6 STAD START Detect Bit 5 RWST Read/Write Status Bit (only for Slave mode) 4 LBST Last Byte Status Bit 3 IRQP IRQ Pending Bit 2 OVST Overflow Status Bit 1 WCO Writing Collision Bit 0 ADDR ADDR

0xc

RESERVED31_8 8 24 SDAD Slave Device Address 1 7 RWCM Read/Write Control or Match 0 DAT DAT

0x10

RESERVED31_8 8 24 TXRXDAT Transmit/Receive Data 0 8 INTC INTC

0xb0020000

PD PD

0x0

MSK MSK

0x4

CFG CFG0

0x8

CFG1

0xc

CFG2

0x10

EXTCTL EXTCTL

0x14

IR IR

0xb0160010

KEY KEY

0xb01a0000

MCA MCA

0xb0080000

CTL CTL

0x0

MHA MHA

0xb00c0000

CTL CTL

0x0

CFG CFG

0x4

DCSCLx DCSCL0

0x10

DCSCL1

0x14

DCSCL2

0x18

DCSCL3

0x1c

QSCL QSCL

0x20

NAND NAND

0xb00a0000

CTL CTL

0x0

STATUS STATUS

0x4

FIFOTIM FIFOTIM

0x8

CLKCTL CLKCTL

0xc

BYTECNT BYTECNT

0x10

ADDR01 ADDR01

0x14

ADDR23 ADDR23

0x18

ADDR45 ADDR45

0x1c

ADDR67 ADDR67

0x20

BUF BUF0

0x24

BUF1

0x28

CMD CMD

0x2c

ECCCTL ECCCTL

0x30

HAMECC HAMECC0

0x34

HAMECC1

0x38

HAMECC2

0x3c

HAMCEC HAMCEC

0x40

RSE RSE0

0x44

RSE1

0x48

RSE2

0x4c

RSE3

0x50

RSPS RSPS0

0x54

RSPS1

0x58

RSPS2

0x5c

FIFODATA FIFODATA

0x60

DEBUG DEBUG

0x70

PCM PCM

0xb0150000

PCNT The base address is not clear! PCNT

0xb003c000

CTL CTL

0x0

PCx PC0

0x4

PC1

0x8

PMU PMU

0xb0000000

CTL CTL

0x0

LBRM 31 VCVS 28 3 LBNM 27 VDVS 24 3 VCDE 23 VCVD 20 3 VDDE 19 VDVD 16 3 BLEN 15 VCOE 14 LA6E 13 LA4E 12 IBIAS 10 2 OSCFREQ 8 2 DC1M 7 DC2M 6 BLVS 3 3 VDV0 2 PWRM 0 2 LRADC LRADC

0x4

RESERVED31_28 28 4 REMOADC4 24 4 RESERVED23_20 22 2 BATADC6 16 6 RESERVED15_14 14 2 TEMPADC6 8 6 RESERVED7_0 0 8 CHG CHG

0x8

EN 31 CURRENT 28 3 CURRENT_50mA 0x0 CURRENT_100mA 0x1 CURRENT_150mA 0x2 CURRENT_200mA 0x3 CURRENT_250mA 0x4 CURRENT_300mA 0x5 CURRENT_400mA 0x6 CURRENT_500mA 0x7 STAT 27 DISCHARGING 0x0 CHARGING 0x1 CHGPHASE 25 2 RESERVED 0x0 PRECHARGE 0x1 CC 0x2 CV 0x3 RESERVED24_16 16 9 PBLS 15 PPHS 14 RESERVED13 13 PDUT 8 5 RESERVED7 7 BLV0 6 TMPSET 4 2 TEMP_40C 0x0 TEMP_45C 0x1 TEMP_50C 0x2 TEMP_55C 0x3 LBNMIVS 2 2 VOLTAGE_2_9 0x0 VOLTAGE_3_1 0x1 VOLTAGE_3_3 0x2 VOLTAGE_3_5 0x3 LBRVS 0 2 VOLTAGE_2_7 0x0 VOLTAGE_2_9 0x1 VOLTAGE_3_1 0x2 VOLTAGE_3_3 0x3 RTCWDT RTC

0xb0018000

CTL CTL

0x0

DHMS DHMS

0x4

RESERVED31_27 27 5 DAY 24 3 RESERVED23_21 21 3 HOUR 16 5 RESERVED15_14 14 2 MIN 8 6 RESERVED7_6 6 2 SEC 0 6 YMD YMD

0x8

RESERVED31 31 CENT 24 7 RESERVED23 23 YEAR 16 7 RESERVED15_12 12 4 MON 8 4 RESERVED7_5 5 3 DATE 0 5 DHMSALM DHMSALM

0xc

RESERVED31_21 21 11 HOURAL 16 5 RESERVED15_14 14 2 MINAL 8 6 RESERVED7_6 6 2 SECAL 0 6 YMDALM YMDALM

0x10

RESERVED31_23 23 9 YEARAL 16 7 RESERVED15_12 12 4 MONAL 8 4 RESERVED7_5 5 3 DATEAL 0 5 WDCTL WDCTL

0x14

TxCTL T0CTL

0x18

T1CTL

0x20

Tx T0

0x1c

T1

0x24

SD SD

0xb00b0000

CTL CTL

0x0

CMDRSP CMDRSP

0x4

RW RW

0x8

FIFOCTL FIFOCTL

0xc

CMD CMD

0x10

ARG ARG

0x14

CRC7 CRC7

0x18

RSPBUFx RSPBUF0

0x1c

RSPBUF1

0x20

RSPBUF2

0x24

RSPBUF3

0x28

RSPBUF4

0x2c

DAT DAT

0x30

CLK CLK

0x34

BYTECNT BYTECNT

0x38

SDR SDR

0xb0070000

CTL CTL

0x0

ADDRCFG ADDRCFG

0x4

EN EN

0x8

RESERVED31_1 1 31 EN 0 CMD CMD

0xc

STAT STAT

0x10

RFSH RFSH

0x14

MODE MODE

0x18

MOBILE MOBILE

0x1c

SPDIF SPDIF

0xb0140000

SPI SPI

0xb0190000

SRAMOC SRAMOC

0xb0030000

CTL CTL

0x0

STAT STAT

0x4

TP TP

0xb0120000

UART UART 1

0xb0160000

0xb0160020

UDC CAST cusb2-otg IP core UDC

0xb00e0000

EP0BC OUT0BC

0x0

IN0BC

0x1

ep0 byte count register RESERVED 8 24 BC 0 8 EP0CS EP0CS

0x2

RESERVED 8 24 OUT_BUSY 3 IN_BUSY 2 NAK Writing 1 clears 1 STALL 0 BCL OUT1BCL

0x8

IN1BCL

0xc

OUT2BCL

0x10

IN2BCL

0x14

Endpoint byte count LSB register BCH OUT1BCH

0x9

IN1BCH

0xd

OUT2BCH

0x11

IN2BCH

0x15

Endpoint byte count MSB CON OUT1CON

0xa

IN1CON

0xe

OUT2CON

0x12

IN2CON

0x16

Endpoint configuration register EP_ENABLE 7 STALL 6 EP_TYPE 2 2 RESERVED 0x0 ISOCHRONOUS 0x1 BULK 0x2 INTERRUPT 0x3 SUBFIFOS 0 2 SINGLE 0x0 DOUBLE 0x1 TRIPLE 0x2 QUAD 0x3 CS OUT1CS

0xb

IN1CS

0xf

OUT2CS

0x13

IN2CS

0x17

Endpoint status register AUTO 4 NPACK1 3 NPACK0 2 BUSY 1 ERROR 0 FIFODAT FIFO1DAT

0x84

FIFO2DAT

0x88

Endpoint FIFO EP0DAT EP0INDAT

0x100

EP0OUTDAT

0x140

Endpoint 0 buffers each 64 bytes long. SETUPDAT SETUPDAT

0x180

SETUP packet buffer EPIRQ IN04IRQ

0x188

OUT04IRQ

0x18a

Endpoint irq flag register EP_NUM 0 3 USBIRQ USBIRQ

0x18c

General usb core irq flags HS Enter high speed operation. Set by core on connection. 5 RESET Asserted on usb reset. 4 SUSPEND 3 SETUP_TOKEN 2 SOF 1 SETUP_DATA Setup data are ready to be accessed in SETUPDAT buffer. 0 EPIEN IN04IEN

0x194

OUT04IEN

0x196

Endpoint interrupt enable register EP_NUM 0 3 USBIEN USBIEN

0x198

General usb interrupts enable register HS 5 RESET 4 SUSPEND 3 SETUP_TOKEN 2 SOF 1 SETUP_DATA 0 IVECT IVECT

0x1a0

Interrupt vector register known (guessed) values: 0x00 - SETUP 0x10 - RESET 0x14 - HS 0x28 - EPs 0xD8 - OTG ENDPRST ENDPRST

0x1a2

Endpoint reset register FIFO_RESET 6 TOGGLE_RESET 5 DIR 4 OUT 0x0 IN 0x1 EP_NUM 0 3 USBCS USBCS

0x1a3

SOFT_CONNECT 6 SIGRESUME 5 USBSPEED 1 HCLSMODE 0 FIFOCTRL FIFOCTRL

0x1a8

CPU_ACCESS 7 DMA 5 DIR 4 OUT 0x0 IN 0x1 EP_NUM 0 3 OTGIRQ OTGIRQ

0x1bc

PERIPH 4 VBUSERR 3 LOCSOFT 2 SPRDET 1 OTG_IDLE 0 OTGSTATUS OTGSTATUS

0x1bf

OTGIEN OTGIEN

0x1c0

OTG interrupt enable register HCMAXPCKL HCIN1MAXPCKL

0x1e2

HCOUT2MAXPCKL

0x3e4

High speed max packed size LSB STADDR OUT1STADDR

0x304

IN2STADDR

0x348

Endpoint buffer start address USBEIRQ USBEIRQ

0x400

USB extended irq register USB 7 WAKEUP 6 RESUME 5 CONDISCON 4 USBIEN 3 WAKEUPIEN 2 RESUMEIEN 1 CONDISCONIEN 0 USBERST USBERST

0x404

DMAEPSEL DMAEPSEL

0x40c

EP_SEL 0 32 UNKNOWN 0x0 EP1_IN 0x1 EP1_OUT 0x3 EP2_IN 0x4 EP2_OUT 0xc YUV2RGB YUV2RGB

0xb00f0000

CTL CTL

0x0

RESERVED 22 10 RFBM Read fifo block mode. 21 WFBM Write fifo block mode 20 EN RGB Decoder enable. 19 FES Fifo empty status. 18 WDCS Write Data/Command Select 16 2 CMD Write LCD register address 0x0 DATA Write LCD register data 0x1 RGB RGB565 Data FrameBuffer Transfer 0x2 YUV YCbCr/YUV Data FrameBuffer Transfer 0x3 DEST RGB Decoder Destination. 15 FORMATS RGB Format 11 3 RGB565_1 16bit (RGB 565 1transfer) 0x0 RGB666_1 18bit (RGB 666 1transfer) 0x1 RGB565_2 8bit (RGB 565 2transfers) 0x2 RGB666_2 9bit (RGB 666 2transfers) 0x3 RGB888_3 8bit (RGB 888 3transfers) 0x4 RGB666_3 6bit (RGB 666 3transfers) 0x5 SEQ RGB Sequence 10 RGB 0x0 BGR 0x1 FWCS FIFO write channel select. 9 SPECIAL 0x0 AHB 0x1 FRCS FIFO read channel select 8 SPECIAL 0x0 AHB 0x1 EMDE FIFO Empty (Write) DRQ Enable. 7 EMIE FIFO Empty (Write) IRQ Enable. 6 FUDE FIFO Full (Read) DRQ Enable. 5 FUIE FIFO Full (Read) IRQ Enable. 4 EMCO FIFO Empty (Write) Condition. 3 EMPTY_4_8 0x0 EMPTY_0_8 0x1 EMIP FIFO Empty (Write) IRQ Pending Bit. 2 FUIP FIFO Full (Read) IRQ Pending Bit. 1 ERP FIFO Error Pending Bit. Write 1 to the bit to clear it and reset the FIFO. 0 FIFODATA FIFODATA

0x4

CLKCTL CLKCTL

0x8

FRAMECOUNT FRAMECOUNT

0xc