vsoc2000 Virtual SOC 2000 Virtual SoC 2000 is a nice chip. Its quad-core architecture with trustzone makes it super powerful. Amaury Pouly ARM 0.5 int Interrupt Collector The interrupt collector controls the routing of the interrupts to the processors. It has 32 interrupts sources, which can be routed as FIQ or IRQ to the either processor. ICOLL Interrupt collector
0x80000000
 ctrl Control register CTRL
0x0
 8 CLKGATE Clock gating control. This bit can be protected by TZ lock. 7 SFTRST Soft reset, the bit will automatically reset to 0 when reset is completed. This bit can be protected by TZ lock. 6 TZ_LOCK Trust Zone lock 5 UNLOCKED 0x0 LOCKED When the interrupt collector is locked, only a secured processor can modify protected fields. 0x1 set 4 clr 8 status Interrupt status register STATUS
0x10
 read-only STATUS Bit is set to 1 is the interrupt is pending. Secured interrupts can only be polled by secured processors (non-secure will always read 0 for those). 0 32 clear Interrupt clear register CLEAR
0x14
 write-only CLEAR Write 1 to clear a pending interrupt. Secured interrupts can only be cleared by secured processors. 0 32 enable Interrupt enable register ENABLE 0 32 0x20 0x10 16 This register controls the routing of the interrupt CPU3_PRIO Interrupt priority 14 2 MASKED Interrupt is masked 0x0 LOW 0x1 HIGH 0x2 NMI Interrupt is non maskable 0x3 CPU3_TYPE Interrupt type 13 IRQ 0x0 FIQ 0x1 CPU3_TZ Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts. 12 CPU2_PRIO 10 2 MASKED Interrupt is masked 0x0 LOW 0x1 HIGH 0x2 NMI Interrupt is non maskable 0x3 CPU2_TYPE Interrupt type 9 IRQ 0x0 FIQ 0x1 CPU2_TZ Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts. 8 CPU1_PRIO Interrupt priority 6 2 MASKED Interrupt is masked 0x0 LOW 0x1 HIGH 0x2 NMI Interrupt is non maskable 0x3 CPU1_TYPE Interrupt type 5 IRQ 0x0 FIQ 0x1 CPU1_TZ Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts. 4 CPU0_PRIO Interrupt priority 2 2 MASKED Interrupt will never be sent to the CPU 0x0 LOW 0x1 HIGH 0x2 NMI Interrupt is non maskable 0x3 CPU0_TYPE Interrupt type 1 IRQ 0x0 FIQ 0x1 CPU0_TZ Trust Zone interrupt: when set, only a secured processor can modify the parameters for secured interrupts. 0 set 4 clr 8 gpio GPIO controller A GPIO controller manages several ports. CPU_GPIO CPU GPIO controllers 1 through 7 1 8 0x80001000+(n-1)*0x1000 port GPIO port PORT 0 2 0x0 0x100 input Input register IN
0x0
 8 VALUE 0 8 output_enable Output enable register OE
0x10
 8 ENABLE 0 8 set 4 clr 8 tog 12 tz Trust Zone TZ
0xa0000000
 ctrl Control Register CTRL
0x0
 8 SCRATCH TZ protected scratch value 4 4 DISABLE One bit per CPU: set to 1 to prevent the processor from being able to enter TZ mode. Can only be set by a secured processor. By default all processors can enter TZ mode. 0 4 debug Debug register DEBUG Debug register Don't touch it! 42
0x50
0x60
0x90
0x110
0x130
 8 read-only